Memory with synchronous bank architecture

A synchronous bank memory comprising:

• a plurality of banks including of a plurality of 1-port memory cells;
• a clock generator which generates an internal clock signal and sends the internal clock signal to said plurality of banks;
• registers and buffers which receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal;
• an access conflict management circuit which receives the address signals from said registers and buffers and generates the port block signal when an access conflict occurs;
• and
• a crossbar switching network, provided between said registers and buffers and said plurality of banks, performing switching at cross points at a plurality of nodes, each of the nodes being located between a line connected to the ports and signal lines from said banks, wherein said crossbar switching network receives the read/write signal and the address signal from said registers and buffers and the data signal from said registers and buffers or said plurality of banks, activates one of the cross points based on the address signal when no port block signal is outputted by said access conflict management circuit.

A synchronous bank memory comprising:

• a plurality of banks including of a plurality of 1-port memory cells;
• a clock generator which generates an internal clock signal and sends the internal clock signal to said plurality of banks;
• registers and buffers which receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal;
• an access conflict management circuit which receives the address signals from said registers and buffers and generates the port block signal when an access conflict occurs;
• and
• a plurality of crossbar switching networks provided between said registers and buffers and a plurality of clusters into which said plurality of banks are divided, wherein each of said plurality of crossbar switching networks performs switching at cross points at nodes, each of the nodes being located between lines connected to the ports and a signal line from each bank in a cluster;
• wherein each of said crossbar switching networks receives the read/write signal and the address signal from said registers and buffers and the data signal from said registers and buffers or said plurality of banks, activates a cross point based on the address signal when no port block signal is outputted by said access conflict management circuit.

A synchronous bank memory comprising:

• a plurality of banks including a plurality of 1-port memory cells;
• a clock generator which generates an internal clock signal and sends the internal clock signal to said plurality of banks;
• registers and buffers which receive a read/write signal and an address signal from each of external ports, receive and send a data signal to and from each of the external ports, and receive and send a port block signal;
• an access conflict management circuit which receives the address signals from said registers and buffers and generates the port block signal when an access conflict occurs;
• and
• a network provided between said registers and buffers and said plurality of banks, wherein said network receives the read/write signal and the address signal from said registers and buffers and the data signal from said registers and buffers or said plurality of banks, generates a bank selection signal when no port block signal is outputted by said access conflict management circuit, and activates the bank selected by the bank selection signal.

A synchronous bank memory comprising:

• a plurality of banks including a plurality of 1-port memory cells;
• a clock generator which generates an internal clock signal and sends the internal clock signal to said plurality of banks;
• registers and buffers which receive a read/write signal and an address signal from external ports, receive and send a data signal to and from external ports, and receive and send a port block signal;
• and
• a network, provided between said registers and buffers and said plurality of banks, wherein said network receives the read/write signal and the address signal from said registers and buffers, generates a bank selection signal to activate the bank selected by the bank selection signal.