MicroTLB and micro tag for reducing power in a processor

A method comprising:

• accessing, with a first virtual address, a first translation lookaside buffer (TLB) configured to store a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB;
• in response to a hit by the first virtual address in the first TLB, accessing a tag circuit configured to identify a plurality of cache lines that are stored in a cache and are within the plurality of virtual pages, the tag circuit storing an in-page portion of one or more virtual addresses corresponding to the one or more of the plurality of cache lines identified by the tag circuit;
• detecting a hit by the first virtual address in the first TLB and the tag circuit, wherein detecting the hit in the tag circuit comprises comparing the in-page portion of the one or more virtual addresses to a corresponding in-page portion of the first virtual address;
• and
• in response to the hit by the first virtual address in the first TLB and the tag circuit, preventing a read of a tag memory in the cache.

A processor comprising:

• a cache comprising a data memory configured to store a plurality of cache lines and a tag memory configured to store a plurality of tags, each of the plurality of tags corresponding to a respective one of the plurality of cache lines;
• and
• a tag circuit configured to detect a hit in the cache by a first virtual address for a subset of the plurality of cache lines;
• and
• in response to a hit by the first virtual address in the tag circuit, the tag circuit is configured to prevent a read of the tag memory, and wherein the data memory is configured to output at least a portion of a first cache line corresponding to the first virtual address.