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US 7,117,289 B2Granted
Claiming cycles on a processor bus in a system having a PCI to PCI bridge north of a memory controller
AssigneeIntel Corporation
InventorVarghese George
Life of this patent
Estimating the term…
Abstract
In one embodiment, the invention provides a method comprising determining information about an input/output device located north of the memory controller; and controlling a response of the memory controller to read/write requests on a processor bus to a bus agent on a system bus south of the memory controller based on the information.
Claims18
A method comprising:
- determining information about a first agent coupled to a processor bus and integrated on a central processing unit, the first agent having registers associated with use of the processor bus;
- replicating the information about the first agent onto a shadow register on a memory controller;
- controlling a response of the memory controller to read/write requests on a processor bus to a bus agent based on the information on the shadow register, and
- automatically updating the shadow register when the registers are written to for a logical peripheral components/interconnect (PCI) bus.
1 more element
A system comprising:
- a processor bus;
- a first agent coupled to the processor bus and integrated on a central processing unit, the first agent having registers associated with use of the processor bus;
- and
- a memory controller coupled to the processor bus, the memory controller having shadow registers that maintain a copy of the information on the registers on the first agent, wherein the shadow registers are updated upon a write command issued for registers for a logical PCI bus.
1 more element
Dependencies are inferred from the claim text.