Circuit, system, and method for data transfer control for enhancing data bus utilization

An information processing system for carrying out data transfer by using a plurality of bus masters, comprising:

• a peripheral apparatus;
• a data bus connected to a peripheral apparatus, said data bus having a plurality of unit data buses, each of which transfers data concurrently;
• a plurality of bus masters connected to each of the unit data buses and configured to send a bus request signal requesting to acquire a use of each of said unit data buses and to transfer data on said unit data buses requested when a request by means of said bus request signal is granted;
• and
• one bus controller connected to all of the bus masters and configured to split-control said unit data buses for said plurality of bus masters by giving a grant signal to the bus masters, which grants the use of each of said unit data buses in accordance with said bus request signal, wherein
• the bus request signal is sent to said bus controller prior to data transfer and has a field comprising a plurality of bits for specifying necessary bit width, each of which said plurality of bits identifying respective one of said unit data buses, and said bus controller grants the use of each of said unit data buses specified by the bits of said bus request signal.

A method of carrying out data transfer through a data bus having a plurality of unit data buses by using a plurality of bus masters, comprising:

• generating a bus request signal requesting to acquire a use of each of unit data buses in each of a plurality of bus masters connected to each of the unit data buses and sending said each bus request signal to a bus controller connected to all of the bus masters prior to data transfer, said data bus being connected to a peripheral apparatus and each of said unit data buses transfers data concurrently;
• sending, in response to said bus request signal, a grant signal granting the use of each of said unit data buses to the bus masters in accordance with said bus request signal;
• and
• occupying said unit data buses granted by said grant signal, and carrying out data transfer by using the unit data buses thus occupied, wherein
• the bus request signal has a field comprising a plurality of bits for specifying necessart bit width, each of said plurality of bits identifying a respective one of said unit data buses, and said bus controller grants the use of each of said unit data buses specified by the bits of said bus request signal.

A data transfer control circuit for carrying out data transfer by using a plurality of bus masters, comprising:

• a data bus connected to a peripheral apparatus, said data bus having a plurality of unit data buses, each of which transfers data concurrently;
• a plurality of bus masters connected to each of the unit data buses and configured to send a bus request signal requesting to acquire a use of each of said unit data buses and to transfer data on said unit data buses requested in response to a bus master select signal which indicates the current bus master to which said grant signal is given;
• and
• one bus controller connected to all of the bus masters and configured to split-control said unit data buses for said plurality of bus masters by giving a grant signal to the bus masters, which grants the use of each of said unit data bus in accordance with said bus request signal, and sending said bus master select signal to each of said bus masters, wherein
• the request signal is sent to said bus controller prior to data transfer has a field comprising a plurality of bits for specifying necessary bit width, each of said plurality of bits identifying a respective one of said unit data buses, and said bus controller grants the use of each of said unit buses specified by the bits of said bus request signal.

An information processing system for carrying out data transfer by using a plurality of bus masters, comprising:

• a peripheral apparatus;
• a data bus connected to a peripheral apparatus, said data bus having a plurality of unit data buses, each of which transfers data concurrently;
• a plurality of bus masters connected to each of the unit data buses and configured to send a bus request signal requesting to acquire a use of each of said unit data buses and to transfer data on said unit data buses requested in response to a bus master select signal which indicates the current bus master to which said grant signal is given;
• and
• one bus controller connected to all of the bus masters and configured to split-control said unit data buses for said plurality of bus masters by giving a grant signal to the bus masters, which grants the use of each of said unit data buses in accordance with said bus request signal, and sending said bus master select signal to each of said bus masters, wherein
• the request signal is sent to said bus controller prior to data transfer and has a field comprising a plurality of bits, each of said plurality of bits corresponding to a respective one of said unit data buses for specifying necessary bit width, and said bus controller grants the use of each of said unit buses specified by the bits of said bus request signal.

A method of carrying out data transfer through a data bus having a plurality of unit data buses by using a plurality of bus masters, comprising:

• generating a bus request signal requesting to acquire a use of each of unit data buses in each of a plurality of bus masters connected to each of the unit data buses and sending, in response to a bus master select signal which indicates the current bus master to which said grant signal is given, said each bus request signal to a bus controller connected to all of the bus masters prior to data transfer, said data bus being connected to a peripheral apparatus and each of said unit data buses transferring data concurrently;
• sending, in response to said bus request signal, a grant signal granting the use of each of said unit data buses to the bus masters in accordance with said bus request signal, and sending said bus master select signal to each of said bus masters;
• and
• occupying said unit data buses granted by said grant signal, and carrying out data transfer by using the unit data buses thus occupied, wherein
• the request signal has a field comprising a plurality of bits for specifying necessary but width, each of said plurality of bits identifying a respective one of said unit data buses, and said bus controller grants the use of each of said unit buses specified by the bits of said bus request signal.

A data transfer control circuit for carrying out data transfer by using a plurality of bus masters, comprising:

• a data bus connected to a peripheral apparatus, said data bus having a plurality of unit data buses, each of which transfers data concurrently;
• a plurality of bus masters connected to each of the unit data buses and configured to send a bus request signal requesting to acquire a use of each of said unit data buses prior to data transfer, and to transfer data on said unit data buses requested when a request by means of said bus request signal is granted;
• and
• one bus controller connected to all of the bus masters and configured to split-control said unit data buses for said plurality of bus masters by giving a grant signal to the bus masters, which grants the use of each of said unit data buses in accordance with said bus request signal, wherein
• the request signal has a field comprising a plurality of bits, each of said plurality of bits identifying a respective one of said unit data buses, and
• said bus master sends the bus request signal to another bus master and the bus controller, and the other bus master determines the availability of each of the unit data buses based on the bus request signal to send the bus request signal specifying available unit data bus.