Method and apparatus for providing packed shift operations in a processor

A method for supporting a packed shift operation, the method comprising:

• augmenting a decoder to receive a control signal of a packed instruction format that can specify a variable data size, an operation type, a first source operand, and a second source operand;
• augmenting a storage location corresponding to the first source operand to hold a first packed data having a set of source data elements of a size specified by the variable data size;
• augmenting said decoder to generate a decoded signal including a first field of control bits indicating a first number of bits less than or equal to the variable data size and corresponding to a comparison between the second source operand and the variable data size, and a second field of one or more select bits according to the operation type;
• augmenting a shifter with a correction circuit to produce a set of destination data elements corresponding to the set of source data element, said decoder coupled with the correction circuit to select, according to the second field of one or more select bits, a corresponding replacement bit for each element of the set of source data elements to correct said first number of bits in each element of the set of destination data elements according to the first field of control bits.

A system comprising:

• a memory to hold a plurality of data elements;
• a processor to perform operations specified by a packed data instruction set having a format identifying a variable data size, an operation type, a first source operand, and a second source operand, said processor including:
• a storage location corresponding to the first source operand to hold a first packed data having a set of source data elements of a size specified by the variable data size;
• a decoder to receive a control signal in the format of the packed data instruction set and to generate a decoded signal including a first field of control bits indicating a first number of bits less than or equal to the variable data size and corresponding to a comparison between the second source operand and the variable data size, and a second field of one or more select bits according to the operation type;
• a correction circuit to produce a set of destination data elements corresponding to the set of source data element, said decoder coupled with the correction circuit to select, according to the second field of one or more select bits, a corresponding replacement bit for each element of the set of source data elements to correct said first number of bits in each element of the set of destination data elements according to the first field of control bits;
• a bus coupled with the processor to transmit data to and from the processor and to and from the memory;
• and
• an interface to couple the bus with one or more devices to provide data to or receive data from the bus, said one or more devices comprising an audio device selected from the group consisting of an audio digitizing device, a sound recording device, a sound playback device, a microphone, a digital-to-analog converter, and a speaker.