US 7,117,143 B2Granted

Clock distribution in a circuit emulator

AssigneeFortelink, Inc.

InventorsMing Yang Wang, Sweyyan Shei, Vincent Chiu

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Abstract

Before using a netlist description of an integrated circuit as a basis for programming a circuit emulator, a clock analysis tool analyzes the netlist to identify synchronizing circuits including clocked devices (“clock sinks”) such a flip-flops, registers and latches for synchronizing communication between blocks of logic within the IC. The tool initially classifies the clock signal input to each clock sink according to its clock domain, sub-domain and phase. The tool then classifies each synchronizing circuit according to relationships between the classifications of the clock signals it employs to clock its input and output clock sinks. The tool then determines, based on the classification of each synchronizing circuit, whether the emulator can reliably emulate that synchronizing circuit, or whether the tool should automatically modify the netlist description of the synchronizing circuit so that the emulator can emulate it. The tool also generates a warning when an emulator may not reliably emulate a synchronizing circuit and the tool cannot automatically modify it so that the emulator can reliably emulate it.

Claims26

Dependent claims

A method for programming an emulator to emulate an integrated circuit (IC) clocked by at least one primary clock signal provided as input to the IC, the IC being described by a netlist as including logic blocks that communicate through synchronizing circuits, wherein the synchronizing circuits include input clock sinks for conveying input signals into logic blocks and output clock sinks for conveying output signals out of logic blocks, and wherein the synchronizing circuits employ clock signals derived from the at least one primary clock signal to clock the input and output clock sinks, the method comprising the steps of:

a. analyzing the netlist to determine a domain, a sub-domain and a phase of each clock signal each synchronizing circuit employs to clock its input and output clock sinks;
b. analyzing the netlist to determine a type of each synchronizing circuit based on relationships between the determined domain, sub-domain and phase of the clock signals the synchronizing circuit employs to clock its input and output sinks, wherein synchronizing circuit types comprise:
at least one type A synchronizing circuit wherein clock signals that clock the synchronizing circuit's input and output clock sinks are derived from at the least one primary clock signal provided as input to the IC and are of similar domain, similar sub-domain and similar phase, and
at least one type B synchronizing circuit wherein clock signals that clock the synchronizing circuit's input and output sinks are derived from the at least one primary clock signal provided as input to the IC and are of similar domain, dissimilar subdomain, and similar phase, and
c. modifying the netlist description of each type B synchronizing circuit so that it becomes a type A synchronizing circuit wherein clock signals that clock the synchronizing circuit's input and output sinks are derived from the at least one primary clock signal provided as input to the IC and are of similar domain, similar subdomain, and similar phase.

2 more elements

Computer-readable media storing instructions which, when read and executed by a computer causes the computer to carry out a method for programming an emulator to emulate an integrated circuit (IC) clocked by at least one primary clock signal provided as input to the IC, the IC being described by a netlist as including logic blocks that communicate through synchronizing circuits, wherein the synchronizing circuits include input clock sinks for conveying input signals into logic blocks and output clock sinks for conveying output signals out of logic blocks, and wherein the synchronizing circuits employ clock signals derived from the at least one primary clock signal to clock the input and output clock sinks, the method comprising the steps of:

a. analyzing the netlist to determine a domain, a sub-domain and a phase of each clock signal each synchronizing circuit employs to clock its input and output clock sinks;
b. analyzing the netlist to determine a type of each synchronizing circuit based on relationships between the determined domain, sub-domain and phase of the clock signals the synchronizing circuit employs to clock its input and output sinks, wherein synchronizing circuit types comprise:
at least one type A synchronizing circuit wherein clock signals that clock the synchronizing circuit's input and output clock sinks are derived from at the least one primary clock signal provided as input to the IC and are of similar domain, similar sub-domain and similar phase, and
at least one type B synchronizing circuit wherein clock signals that clock the synchronizing circuit's input and output sinks are derived from the at least one primary clock signal provided as input to the IC and are of similar domain, dissimilar subdomain, and similar phased and
c. modifying the netlist description of each type B synchronizing circuit so that it becomes a type A synchronizing circuit wherein clock signals that clock the synchronizing circuit's input and output sinks are derived from the at least one primary clock signal provided as input to the IC and are of similar domain, similar sub-domain, and similar phase.

2 more elements

Dependencies are inferred from the claim text.