US 7,116,881 B1Granted

CMOS process polysilicon strip loaded waveguides with a three layer core

AssigneeLuxtera, Inc.

InventorsLawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier

Life of this patent

Estimating the term…

Loading patent…

Abstract

A standard CMOS process is modified to fabricate optical, optoelectronic and electronic devices at the same time on a monolithic integrated circuit. A polysilicon strip loaded waveguide is used as an example to illustrate the invention. The waveguide has a three layer core made of a polysilicon strip on a silicon slab with a silicon dioxide layer between the strip and the slab. In a standard CMOS process, a layer of metallic salicide is deposited for metallic contacts for electronic components, such as transistors. In the present invention, prior to the deposition of the salicide, a salicide blocking layer is selectively deposited for protecting silicon waveguide against damages. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide.

Claims18

Dependent claims

An optical waveguide on a substrate, where the optical waveguide is comprised of:

a core comprised of:
a slab of monocrystalline silicon, where the slab and a silicon body of a transistor are formed from the same layer of monocrystalline silicon on the same substrate,
a layer of dielectric material disposed on the slab of monocrystalline silicon, where the layer of dielectric material and a gate oxide for a transistor are formed at the same time of the same dielectric material, and
a strip of polysilicon disposed on the layer of dielectric material, where the strip and a polysilicon gate for a transistor are formed at the same time from the same polysilicon, and
a cladding comprised of a plurality of dielectric materials, where at least one of the plurality of dielectric materials is comprised of a salicide block layer used during the fabrication of a transistor on the same substrate.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/177,765Filed 7 Jul 2005 · division
Priority: 24 Jun 2002
Granted: 3 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G02B 6/12004
Of the integrated circuit kind: combinations of two or more optical elements
G02B 6/132
Integrated optical circuits characterised by the manufacturing method: by deposition of thin films
G02B
Optical elements, systems or apparatus

Family

Application60/391,278Us provisional application · filed 24 Jun 2002
Application60/393,489Us provisional application · filed 3 Jul 2002
Application60/393,490Us provisional application · filed 3 Jul 2002
Application60/393,485Us provisional application · filed 3 Jul 2002
Application60/393,683Us provisional application · filed 3 Jul 2002
Application60/393,682Us provisional application · filed 3 Jul 2002
Application10/606,297Parent of this division · filed 24 Jun 2003
US 7,010,208 B1Parent of this division
US 7,116,881 B1This patent

From the US filing history. Foreign family members aren’t listed.