Clock recovery circuit and receiver circuit for improving the error rate of signal reproduction
AssigneeFujitsu Limited
InventorsTakuya Saze, Hirotaka Tamura, Takaya Chiba, Kohtaroh Gotoh, Hideki Ishida
Life of this patent
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Abstract
A clock recovery circuit has a boundary detection/discrimination circuit to detect and discriminate a boundary in an input signal in accordance with a first signal. The clock recovery circuit performs clock recovery by controlling the timing of the first signal in accordance with the detected boundary, wherein boundary detection timing in the boundary detection/discrimination circuit is varied by controlling the first signal.
Claims56
A clock recovery circuit comprising:
- a boundary detection/discrimination circuit for detecting or discriminating a boundary in an input signal in accordance with a first signal, and which performs clock recovery by controlling the timing of said first signal in accordance with said detected boundary, wherein boundary detection timing in said boundary detection/discrimination circuit is varied by controlling said first signal;
- and
- a phase interpolator for delaying said first signal by different times, and wherein modulation is applied on a code supplied to said phase interpolator.
A clock recovery circuit comprising:
- a boundary detection/discrimination circuit for detecting or discriminating a boundary in an input signal in accordance with a first signal, and which performs clock recovery by controlling the timing of said first signal in accordance with said detected boundary, wherein boundary detection timing in said boundary detection/discrimination circuit is varied by controlling said first signal,
- wherein said boundary detection/discrimination circuit includes a plurality of boundary detection units,
- wherein each of said boundary detection units detects a boundary in accordance with a boundary detection unit control signal, and
- wherein said each boundary detection unit detects said boundary in said input signal at a timing variably displaced from the timing at which said boundary should otherwise be detected;
- and
- a plurality of buffers for delaying said boundary detection unit control signals by respectively different times.
A clock recovery circuit comprising:
- a boundary detection/discrimination circuit for detecting or discriminating a boundary in an input signal in accordance with a first signal, and which performs clock recovery by controlling the timing of said first signal in accordance with said detected boundary, wherein boundary detection timing in said boundary detection/discrimination circuit is varied by controlling said first signal,
- wherein said boundary detection/discrimination circuit includes a plurality of boundary detection units,
- wherein each of said boundary detection units detects a boundary in accordance with a boundary detection unit control signal, and
- wherein said each boundary detection unit detects said boundary in said input signal at a timing variably displaced from the timing at which said boundary should otherwise be detected;
- and
- a phase interpolator for delaying said boundary detection unit control signals by respectively different times, and wherein modulation is applied on a code supplied to said phase interpolator.
A clock recovery circuit comprising:
- a boundary detection/discrimination circuit for detecting or discriminating a boundary in an input signal in accordance with a first signal, and which performs clock recovery by controlling the timing of said first signal in accordance with said detected boundary, wherein boundary detection timing in said boundary detection/discrimination circuit is varied by controlling said first signal,
- wherein said boundary detection/discrimination circuit includes a plurality of boundary detection units,
- wherein each of said boundary detection units detects a boundary in accordance with a boundary detection unit control signal, and
- wherein said each boundary detection unit detects said boundary in said input signal at a timing variably displaced from the timing at which said boundary should otherwise be detected;
- and
- a plurality of variable delay circuits for delaying said boundary detection unit control signals by respectively different times.
A receiver circuit comprising:
- a data detection/discrimination circuit for detecting or discriminating data carried in an input signal;
- a boundary detection/discrimination circuit for detecting or discriminating a boundary appearing in said input signal;
- a phase comparator for receiving outputs from said data detection/discrimination circuit and said boundary detection/discrimination circuit, and for comparing the phases of said outputs;
- a clock signal generating circuit for receiving an output from said phase comparator, and for supplying a first internal clock to said data detection/discrimination circuit and a second internal clock to said boundary detection/discrimination circuit;
- and a boundary skew generating circuit for varying boundary detection timing in said boundary detection/discrimination circuit by controlling a skew given to said second internal clock.
A clock recovery circuit for recovering a clock from an input signal by using a phase adjusting timing signal generating circuit in a feedback loop, comprising a displacing circuit for displacing an output of said phase adjusting timing signal generating circuit from an approximate center position of said input signal.
A clock recovery circuit for recovering a clock from an input signal by using a phase adjusting timing signal generating circuit in a feedback loop, comprising a displacing circuit for displacing an output of said phase adjusting timing signal generating circuit from an equispaced phase relationship.
A receiver circuit comprising:
- a data detection/discrimination circuit for detecting or discriminating data carried in an input signal;
- a changing point detection/discrimination circuit for detecting or discriminating a changing point appearing in said input signal;
- a phase comparator circuit for receiving outputs from said data detection/discrimination circuit and said changing point detection/discrimination circuit, and for comparing the phases of said outputs;
- and a clock signal generating circuit for receiving an output from said phase comparator circuit, and for supplying a first internal clock to said data detection/discrimination circuit and a second internal clock to said changing point detection/discrimination circuit, and wherein:
- said receiver circuit includes a displacing circuit for displacing the phase relationship between said first internal clock and said second internal clock from an equispaced phase relationship.
Dependencies are inferred from the claim text.