Method and system for providing clock signals

A device for providing a plurality of clock signals, comprising:

• a first clock circuit operable to:
• receive a first clock signal comprising a plurality of first cycles;
• and
• generate a second clock signal from the first clock signal, the second clock signal comprising a plurality of second cycles, a second cycle of the plurality of second cycles corresponding to a first multiple of the first cycles;
• a second clock circuit operable to:
• receive the first clock signal;
• and
• generate a third clock signal from the first clock signal, the third clock signal comprising a plurality of third cycles, a third cycle of the plurality of third cycles corresponding to a second multiple of the second cycles;
• a clock control coupled to the first clock circuit and the second clock circuit and operable to:
• sample the first clock signal and the second clock signal using the third clock signal;
• and
• determine a safe cycle in response to the sampled first clock signal and the sampled second clock signal;
• and
• a translator coupled to the clock control and operable to transfer data between a first circuit running at the second clock signal and a second circuit running at the third clock signal in accordance with the safe cycle in order to provide the plurality of clock signals.

A system for providing a plurality of clock signals, comprising:

• means for receiving a first clock signal at a first clock circuit and at a second clock circuit, the first clock signal comprising a plurality of first cycles;
• means for generating a second clock signal from the first clock signal at the first clock circuit, the second clock signal comprising a plurality of second cycles, a second cycle of the plurality of second cycles corresponding to a first multiple of the first cycles;
• means for generating a third clock signal from the first clock signal at the second clock circuit, the third clock signal comprising a plurality of third cycles, a third cycle of the plurality of third cycles corresponding to a second multiple of the second cycles;
• means for sampling the first clock signal and the second clock signal using the third clock signal;
• means for determining a safe cycle in response to the sampled first clock signal and the sampled second clock signal;
• and
• means for transferring data between a first circuit running at the second clock signal and a second circuit running at the third clock signal in accordance with the safe cycle in order to provide the plurality of clock signals.

A method for providing a plurality of clock signals, comprising:

• receiving a first clock signal at a first clock circuit and at a second clock circuit, the first clock signal comprising a plurality of first cycles;
• generating a second clock signal from the first clock signal at the first clock circuit, the second clock signal comprising a plurality of second cycles, a second cycle of the plurality of second cycles corresponding to a first multiple of the first cycles;
• generating a third clock signal from the first clock signal at the second clock circuit, the third clock signal comprising a plurality of third cycles, a third cycle of the plurality of third cycles corresponding to a second multiple of the second cycles, the second multiple varying within a specified range;
• sampling the first clock signal and the second clock signal using the third clock signal by detecting an edge of a third cycle of the plurality of third cycles of the third clock signal, sampling the second clock signal approximately when the edge is detected, and sampling the first clock signal approximately when the edge is detected;
• detecting an alpha cycle of the third clock signal in response to the sampled first clock signal and the sampled second clock signal;
• and
• transferring data between a first circuit running at the second clock signal and a second circuit running at the third clock signal in accordance with the safe cycle in order to provide the plurality of clock signals by:
• determining an occurrence of a first safe cycle in accordance with the alpha cycle, the first safe cycle representing a cycle during which the data is to be transferred from the second circuit running at the third clock signal to the first circuit running at the second clock signal, delaying the data from the second circuit running at the third clock signal, and transferring the data during the occurrence of the first safe cycle;
• determining an occurrence of a second safe cycle in accordance with the alpha cycle, the second safe cycle representing a cycle during which the data is to be transferred from the first circuit running at the second clock signal to the second circuit running at the third clock signal, generating a control signal, a cycle of the control signal corresponding to the second safe cycle, and transferring the data from the first circuit running at the second clock signal to the second circuit running at the third clock signal according to the control signal;
• determining a plurality of third safe cycles of the third clock signal corresponding to a second cycle of the second clock signal, a third safe cycle of the plurality of third safe cycles representing a cycle during which the data is to be transferred, the data comprising a request, and transferring the data during a last third safe cycle of the third safe cycles;
• and
• determining a plurality of fourth safe cycles of the third clock signal corresponding to a second cycle of the second clock signal, each fourth safe cycle of the plurality of fourth safe cycles representing a cycle during which the data is to be transferred, the data comprising a response, and transferring the data during a first fourth safe cycle of the safe cycles;
• and
• predicting a predicted occurrence of the alpha cycle, detecting an actual occurrence of the alpha cycle, determining that the actual occurrence and the predicted occurrence are asynchronous, and determining that the first clock circuit and the second clock circuit are asynchronous.