Unified memory address generation system and method for fetching and storing MPEG video data
AssigneeNJR Corporation
InventorsQiong Wu, Kwok K. Chau, Hau-Yung Chen
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Abstract
A method and apparatus is provided for generating various binary addresses for use in decoding MPEG video data. One or more n-bit counters and mutiplexers are used to generate such binary addresses. Different binary addresses can be generated by the same n-bit counter by swapping the bits of the n-bit counter. The number of different binary addresses that an n-bit counter can generate is n factorial.
Claims12
A method for decoding a plurality of video frames, the method comprising the steps of:
- using an n-bit counter to generate up to 2n number of distinct bit pattern sequences, wherein n is a positive integer and wherein each of the 2n distinct bit pattern sequences is associated with a distinct binary value comprising n bits;
- generating up to n factorial number of non-sequential bit pattern sequences from the 2n number of distinct bit pattern sequences by swapping a pair of bits in each of the 2n distinct binary values comprising n bits;
- selecting one or more of the n factorial number of non-sequential bit pattern sequences to create one or more corresponding addressing schemes;
- and
- fetching and storing data that is associated with the plurality of video frames using the one or more addressing schemes.
A computer-readable medium carrying one or more sequences of instructions for decoding data from a plurality of video frames in a computer system, wherein execution of the one or more sequences of instructions by one or more processors causes the one or more processors to perform the steps of:
- using an n-bit counter to generate up to 2n number of distinct bit pattern sequences, wherein n is a positive integer and wherein each of the 2n distinct bit pattern sequences is associated with a distinct binary value comprising n bits;
- generating up to n factorial number of non-sequential bit pattern sequences from the 2n number of distinct bit pattern sequences by swapping a pair of bits in each of the 2n distinct binary values comprising n bits;
- selecting one or more of the n factorial number of non-sequential bit pattern sequences to create one or more corresponding addressing schemes;
- and
- fetching and storing data that is associated with the data from the plurality of video frames using the one or more addressing schemes.
An apparatus for decoding a plurality of video frames, comprising:
- one n-bit counters, wherein the n-bit counter generates up to 2n number of distinct bit pattern sequences, wherein n is a positive integer;
- other address generator circuitry for generating up to n factorial number of non-sequential bit pattern sequences from the 2n number of distinct bit pattern sequences by swapping a pair of bits in each of 2n respectively associated distinct binary values comprising n bits;
- and
- one or more multiplexers corresponding to the n-bit counters for selecting one or more of the n factorial number of non-sequential bit pattern sequences to create one or more corresponding addressing schemes associated with the plurality of video frames.
Dependencies are inferred from the claim text.