Dual port SRAM cell
AssigneeHynix Semiconductor Inc.
InventorByung-Il Hong
Life of this patent
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Abstract
The present invention provides a SRAM that is capable of performing a writing and reading operations simultaneously without collision while reducing size of cell, by providing a dual port SRAM cell. For this, the dual port SRAM cell, including: a writing section having a first transistor for inputting a data input signal from a bit line in response to a control signal from a word line; a data storage section having three transistors for storing the data input signal from the outside through the writing section; and a reading section having two transistors for reading the data input signal stored in the data storage section in response to control signal from a common line.
Claims19
A dual port SRAM cell comprising:
- a writing section having a transistor for inputting a data input signal from a bit line in response to a control signal from a word line;
- a data storage section having only three transistors for storing the data input signal from the outside through the writing section;
- and
- a reading section having two transistors for reading the data input signal stored in the data storage section in response to control signal from a common line.
A dual port SRAM cell, comprising:
- a writing section having a first transistor for inputting a data input signal from a bit line in response to a control signal from a word line;
- a data storage section having only a second, a third and a fourth transistors, wherein the second transistor is coupled to the output port of the first transistor, the third transistor is operated inversely to the second transistor, and the fourth transistor is operated inversely to the third transistor, the output port of the first transistor, the input port of the second transistor, the gate of the third transistor and the gate of the fourth transistor being commonly coupled to a first node and the input port of the third transistor and the output port of the fourth being commonly connected to a second node that is operated to have an inverse signal level to a signal level at the first node;
- and
- a reading section having a fifth and a sixth transistors, wherein the fifth transistor whose gate is coupled to the second node is pull-down operated and the sixth transistor whose gate is operated by a common line is connected to the fifth transistor to form a third node, to output an inverse signal to the signal at the second node in response to the signal from the common line.
A dual port SRAM cell, comprising:
- a first node at which data from a bit line is maintained, wherein the data is inputted from the bit line in response to a control signal from a word line, stored and outputted onto a data line in response to a signal from a common line;
- a second node at which signal level is maintained in an inverse state to the input data at the first node;
- and
- a third node at which a same signal level as maintained at the first node is outputted in response to the signal on the common line.
Dependencies are inferred from the claim text.