Pseudo-synchronization of the transportation of data across asynchronous clock domains
AssigneeVIA Technologies, Inc.
InventorHon Chung Fung
Life of this patent
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Abstract
A pseudo-synchronous temporary storage element transports data between two system blocks with different clock systems by pseudo-synchronizing the clock edges of the two clock signals. The pseudo-synchronization circuit may be an integral part of a storage element, a separate pseudo-synchronization device, or a discrete add-on circuit to an off the shelf storage element device.
Claims19
A method of transporting data between a first device operating at a first frequency and a second device operating at a second frequency comprising:
- pseudo-synchronizing an enable signal from the first device with an enable signal from the second device such that the pseudo-synchronized enable signals can be captured by logic elements operating at either of the first and second clock frequencies;
- reading data enabled by a first pseudo-synchronized enable signal from a first device into a temporary storage element;
- and
- writing data from the temporary storage element to a second device enabled by a second pseudo-synchronized enable signal.
A temporary storage system for transporting data between a first device with a first clock frequency and a second device with a second clock frequency comprising:
- a temporary storage element;
- an input on the temporary storage element to read data into the temporary storage element from a first device;
- an output on the temporary storage element to write data out of the temporary storage element to a second device;
- a plurality of memory locations in the temporary storage element to store the data read into and written out of the temporary storage element;
- a read clock input on the temporary storage element for receiving a read clock with frequency of first device;
- a write clock input on the temporary storage element for receiving a write clock with a frequency of the second device;
- a read enable input in the temporary storage element for receiving a read enable signal;
- a write enable input in the temporary storage element for receiving a write enable signal;
- and
- a pseudo-synchronization circuit to pseudo-synchronize the write enable signal and the read enable signal such that the pseudo-synchronized enable signals can be captured by logic elements operating at either of the first or second clock frequencies.
A temporary storage system for transporting data between a first device and a second device with corresponding first clock frequency and second clock frequency comprising:
- means for pseudo-synchronizing an enable signal from the first device with an enable signal from the second device such that the pseudo-synchronized enable signals can be captured by logic elements operating at either of the first and second clock frequencies;
- means for reading data enabled by a first pseudo-synchronized enable signal from the first device into a temporary storage element;
- and
- means for writing data from the temporary storage element to the second device enabled by a second pseudo-synchronized enable signal.
A pseudo-synchronization circuit comprising:
- a first exclusive OR gate;
- a first flip-flop communicatively coupled to the first exclusive OR gate;
- a second flip-flop communicatively coupled to the first flip-flop;
- a second exclusive OR gate communicatively coupled to the second flip-flop;
- a first clock input communicatively coupled to the first flip flop;
- a second clock input communicatively coupled to the second flip flop;
- and
- a control signal input communicatively coupled to the second exclusive OR gate.
Dependencies are inferred from the claim text.