Semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorsYuui Shimizu, Yoshihisa Iwata, Kenji Tsuchida
Life of this patent
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Abstract
A semiconductor memory comprises a memory cell, a pair of reference cells for use in generation of a reference electric potential, a first read circuit which compares a read electric potential obtained from the memory cell with the reference electric potential and determines data in the memory cell, a second read circuit which detects a state of the pair of reference cells and outputs a detection signal indicating the state of the pair of reference cells, and a control circuit which controls a write operation for the pair of reference cells based on the detection signal.
Claims20
A semiconductor memory comprising:
- a memory cell;
- a pair of reference cells for use in generation of a reference electric potential;
- a first read circuit which compares a read electric potential obtained from the memory cell with the reference electric potential and determines data in the memory cell;
- a second read circuit which detects a state of the pair of reference cells and outputs a detection signal indicating the state of the pair of reference cells;
- and
- a control circuit which controls a write operation for the pair of reference cells based on the detection signal.
A semiconductor memory comprising:
- a memory cell;
- a pair of reference cells for use in generation of a reference electric potential;
- a read circuit which, during a read operation, compares a read electric potential obtained from the memory cell with the reference electric potential to determine data in the memory cell, and during a test, detects a state of the pair of reference cells to output a detection signal which indicates the state of the pair of reference cells;
- and
- a control circuit which controls a write operation for the pair of reference cells based on the detection signal.
Dependencies are inferred from the claim text.