High precision reference devices and methods

A non-volatile memory device comprising:

• a plurality of memory elements each adapted to provide data having a logic state;
• a bias stage adapted to bias the memory elements;
• a reference module adapted to provide a reference for each of the memory elements and to provide a threshold reference in response to the references for each of the memory elements;
• a sensing stage to compare the threshold reference and the data from the memory elements to sense the logic state of the data,
• wherein the reference module comprises two transistors connected in a current mirror configuration to receive the reference for each of the memory elements and to provide the threshold reference, and wherein
• the reference module comprises a first, a second, and a third transistor, each having three terminals, and wherein a first terminal of the third transistor is connected to a supply voltage, a second terminal of the third transistor is connected to the averaging stage, and a third terminal of the third transistor is connected to a first terminal of the first transistor.

A method comprising:

• receiving a first cell reference from a first cell and a second cell reference from a second cell, the first and second cells comprising two transistors each having three terminals;
• providing a threshold reference in response to the first and second cell reference
• comparing the threshold reference to a first data bit having a logic state;
• and
• sensing the logic state of the first data bit in response to comparing the threshold reference to the first data bit, wherein
• a first terminal of the first transistor provides a cell reference to an averaging stage, a second terminal of the first transistor receives a first bias voltage, and a third terminal of the first transistor is connected to a first terminal of the second transistor;
• and
• a second terminal of the second transistor receives a second bias voltage and a third terminal of the second transistor is connected to a reference voltage.

A system comprising:

• a logic device coupled to a memory, the memory comprising a plurality of memory elements and a reference stage comprising a plurality of cells each providing a cell reference, each of the cells having two transistor with three terminals;
• a wireless interface coupled to the logic device to enable the logic device to send and receive wireless signals;
• wherein the reference stage provides a threshold reference in response to the cell references, and the memory provides an output in response to the threshold reference and the stored data;
• and
• wherein a first terminal of the first transistor provides a cell reference to an averaging stage, a second terminal of the first transistor receives a first bias voltage, and a third terminal of the first transistor is connected to a first terminal of the second transistor;
• and a second terminal of the second transistor receives a second bias voltage and a third terminal of the second transistor is connected to a reference voltage.