Redundancy circuits and memory devices having a twist bitline scheme and methods of repairing defective cells in the same

Abstract

Redundancy circuits are provided for an integrated circuit memory device including a first memory cell block including a plurality of primary wordlines and a spare wordline, each associated with a plurality of memory cells; a second memory cell block including a plurality of primary wordlines and a spare wordline, each associated with a plurality of memory cells; and a plurality of bitlines extending across both the first and the second memory cell blocks the plurality of bitlines having a twisted bitline structure in which the bitlines are twisted between the first memory cell block and the second memory cell block and are not twisted within the respective memory cell blocks. The redundancy circuit is coupled to the primary and spare wordlines of both the first memory cell block and the second memory cell block. The redundancy circuit is also configured to select the spare wordline of the first memory cell block to replace one of the primary wordlines of the first memory cell block associated with a defective cell and to select the spare wordline of the second memory cell block to replace one of the primary wordlines of the second memory cell block associated with a defective cell so that data stored in spare cells connected to a selected spare wordline have a same data scramble as that of cells connected to the correspond.

Dependencies are inferred from the claim text.