Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM

A write path circuit for a synchronous memory, comprising:

• a delay circuit having an input coupled to a data signal for generating a first and a second delayed data signal, wherein the first and second delayed data signals are differently delayed by the delay circuit;
• a first transmission circuit for passing the first delayed data signal to a rising edge write data line upon the assertion of a strobe signal;
• and
• a second transmission circuit for passing the second delayed data signal to a falling edge write data line upon the assertion of the inverse of the strobe signal.

A write path circuit for a synchronous memory, comprising:

• a delay circuit having an input coupled to a data signal for generating a first and a second delayed data signal, wherein the delay of the first and second delayed data signals are adjustable by the delay circuit;
• a first transmission circuit for passing the first delayed data signal to a rising edge write data line upon the assertion of a strobe signal;
• and
• a second transmission circuit for passing the second delayed data signal to a falling edge write data line upon the assertion of the inverse of the strobe signal.

A write path circuit for a double-data-rate synchronous memory, comprising:

• an input buffer having a data input and an output;
• a first delay element having an input coupled to the output of the input buffer and having an output, the first delay element responsive to a data signal at the output of the input buffer to generate a first delayed data signal;
• a second delay element having an input coupled to the output of the input buffer and having an output, the second delay element responsive to the data signal at the output of the input buffer to generate a second delayed data signal;
• a first pass gate having an input coupled to the output of the first delay element, an output, and at least one control input;
• and
• a second pass gate having an input coupled to the output of the second delay element, an output, and at least one control input,
• wherein the first pass gate is responsive to a rising edge in at least one data strobe signal applied to the at least one control input thereof to present the first delayed data signal on the first pass gate output,
• and wherein the second pass gate is responsive to a falling edge in the at least one data strobe signal applied to the at least one control input thereof to present the second delayed data signal on the second pass gate output.

A write path circuit for a synchronous semiconductor memory device, comprising:

• an input buffer having a data input and an output;
• a delay circuit having an input coupled to the output of the input buffer and having a first output and a second output, the delay circuit responsive to a data signal at the output of the input buffer to generate a first delayed data signal on the first output and a second delayed data signal on the second output,
• a first pass gate having an input coupled to the first output of the delay circuit, an output, and at least one control input;
• and
• a second pass gate having an input coupled to the second output of the delay circuit, an output, and at least one control input,
• wherein the first pass gate is responsive to a rising edge in at least one data strobe signal applied to the at least one control input thereof to present the first delayed data signal on the first pass gate output,
• and wherein the second pass gate is responsive to a falling edge in the at least one data strobe signal applied to the at least one control input thereof to present the second delayed data signal on the second pass gate output.

A method of operating a write path circuit of a synchronous memory device, comprising:

• applying a sequence of data bits to a first delay circuit and a second delay circuit to derive first and second delayed data signals;
• applying the first delayed data signal to a first transmission circuit and the second delayed data signal to a second transmission circuit;
• passing the first delayed data signal to a rising edge write data line upon the assertion of a strobe signal;
• and
• passing the second delayed data signal to a falling edge write data line upon the assertion of the inverse of the strobe signal.

A method of operating a write path circuit of a synchronous memory device, comprising:

• applying a sequence of data bits to a delay circuit;
• deriving a first delayed data signal and a second delayed data signal from the delay circuit, wherein the first and second delayed data signals are differently delayed by the delay circuit;
• passing the first delayed data signal to a rising edge write data line upon the assertion of a strobe signal;
• and
• passing the second delayed data signal to a falling edge write data line upon the assertion of the inverse of the strobe signal.

A method of operating a write path circuit of a synchronous memory device, comprising:

• applying a sequence of data bits to a delay circuit;
• deriving a first delayed data signal and a second delayed-data signal from the delay circuit, wherein the delay of the first and second delayed data signals are adjustable by the delay circuit;
• passing the first delayed data signal to a rising edge write data line upon the assertion of a strobe signal;
• and
• passing the second delayed data signal to a falling edge write data line upon the assertion of the inverse of the strobe signal.

A method of operating a write path circuit of a synchronous double-data rate memory device, comprising:

• applying a clock signal to a clock terminal of the memory device;
• deriving, within the memory device, at least one data strobe signal from the clock signal;
• applying a data signal comprising a sequence of data bits to at least one data terminal of the memory device;
• receiving the data signal in a data buffer;
• applying contents of the data buffer to a first delay element and a second delay element to derive first and second delayed data signals;
• applying the first delayed data signal to a first pass gate input and the second delayed data signal to a second pass gate input;
• opening the first pass gate and closing the second pass gate in response to a rising edge in the at least one data strobe signal;
• and
• closing the first pass gate and opening the second pass gate in response to a falling edge in the at least one data strobe signal.

A method of adjusting a setup and hold window of a data signal relative to a data strobe signal in a synchronous semiconductor memory device, wherein the data signal comprises first and second bits of data applied in succession to a data input terminal of the semiconductor memory device, and wherein the data strobe signal comprises a signal having a rising edge and a falling edge, the method comprising:

• buffering the data signal in a data buffer having an output;
• applying the buffered data signal to a first delay element and to a second delay element to derive first and second delayed data signals each comprising first and second bits of data appearing in succession on respective first and second delayed data lines;
• and
• adjusting the first delay element such that appearance of the first bit of data appears on the first delayed data lines in a predetermined timed relationship with the rising edge, and adjusting the second delay element such that the second bit of data appears on the second delayed data line in a predetermined timed relationship with the falling edge.