Multiple erase block tagging in a flash memory device

A method for parallel erase block tagging a plurality of memory devices each having a plurality of memory blocks including a plurality of memory cells, each memory block having an erase block latch, the method comprising:

• transmitting an erase pulse to each of the plurality of memory blocks of each memory device, wherein only those blocks that are not erase block tagged receive the erase pulse;
• reading the plurality of memory cells to determine the memory erase block status for each of the plurality of memory blocks;
• and
• transmitting a parallel erase block tagging data burst to the plurality of memory devices, the data burst comprising a plurality of erase block tag patterns, each tag pattern for tagging a plurality of memory blocks of each memory device such that the tagged memory blocks cannot receive an erase pulse, each erase block tag pattern indicating which of the erase block latches to set in response to the memory erase block status.

A method for parallel erase block tagging a plurality of memory devices in a testing apparatus, each memory device having a plurality of memory blocks organized into sectors and including a plurality of memory cells, each memory block having an erase block latch, the method comprising:

• transmitting an erase pulse to each of the plurality of memory blocks of each memory device, wherein only those blocks that are not erase block tagged receive the erase pulse;
• reading the plurality of memory cells to determine the memory erase block status for each of the plurality of memory blocks;
• if at least one memory block is still programmed, generating an erase block tag pattern for each memory block still programmed;
• generating a plurality of data bursts, each data burst comprised of erase block tag patterns for a predetermined sector address;
• transmitting the plurality of data bursts in parallel to the plurality of memory devices such that a plurality of memory blocks of each memory device are tagged, each erase block tag pattern indicating which of the erase block latches to set in response to the memory erase block status;
• and
• setting the erase block latches in response to the erase block tag patterns.

An apparatus for parallel erase block tagging comprising:

• a plurality of memory devices, each memory device comprising a plurality of memory blocks, each memory block having an erase block tag latch that prevents erase pulses transmitted to a particular memory block from being received by the memory block;
• a plurality of data input/output lines coupled to the plurality of memory devices;
• and
• a processor coupled to the plurality of data input/output lines for controlling testing operations of the plurality of memory devices, the processor capable of generating data bursts comprising a plurality of erase block tag patterns that are transmitted to a plurality of memory blocks of each of the plurality of memory devices in parallel.

An electronic system for parallel erase block tagging of memory devices, the system comprising:

• a plurality of memory devices, each memory device comprising a plurality of memory blocks, each memory block having an associated erase block tag latch that prevents erase pulses transmitted to a particular memory block from being received by the memory block;
• a plurality of data input/output lines coupled to the plurality of memory devices;
• and
• a processor coupled to the plurality of data input/output lines for controlling testing operations of the plurality of memory devices, the processor capable of transmitting an erase pulse to the plurality of memory blocks that are not erase block tagged, determining a memory erase block status for the plurality of memory blocks, and transmitting a parallel erase block tagging data burst substantially simultaneously to a plurality of memory blocks of each of the plurality of memory devices, the data burst comprising erase block tag patterns for setting an associated erase block tag latch in the plurality of the memory devices.

A method for parallel erase block tagging a plurality of memory devices each having a plurality of memory blocks including a plurality of memory cells, each memory block having an erase block latch, the method comprising:

• transmitting an erase pulse to each of the plurality of memory blocks of each memory device, wherein only those blocks that are not erase block tagged receive the erase pulse;
• reading the plurality of memory cells to determine the memory erase block status for each of the plurality of memory blocks;
• and
• transmitting a parallel erase block tagging data burst to a plurality of memory blocks of each of the plurality of memory devices, the data burst comprising a plurality of erase block tag patterns each having an equivalent logical state such that when the plurality of memory devices receive the erase block tag patterns, the erase block latches are set to a predetermined state.