Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device

A method of programming a memory cell having a floating gate structure in a nonvolatile semiconductor memory device, comprising:

• a first programming step of applying a first program pulse to a memory cell;
• a first verifying step of verifying whether a threshold voltage of said memory cell becomes higher than or equal to a first reference voltage;
• a repeating step of repeating said first programming step until said memory cell passes said first verifying step while progressively increasing a programming capability of said first program pulse, said programming capability being defined by a product of a pulse voltage and a pulse width;
• a second verifying step of verifying whether said threshold voltage of said memory cell becomes higher than or equal to a second reference voltage that is higher than said first reference voltage;
• and
• a second programming step of applying a second program pulse to said memory cell until said memory cell passes said second verifying step while keeping a programming capability of said second program pulse constant.

A nonvolatile semiconductor memory device comprising:

• a plurality of memory cells each of which has a floating gate structure;
• a programming circuit configured to operate in a first programming mode and a second programming mode;
• and
• a verifying circuit configured to verify whether a threshold voltage of a memory cell of said plurality of memory cells becomes higher than or equal to a predetermined voltage,
• wherein said programming circuit applies in said first programming mode a first program pulse to first memory cells of said plurality of memory cells while progressively increasing a programming capability of said first program pulse until said verifying circuit confirms that threshold voltages of said first memory cells become higher than or equal to a first reference voltage, said programming capability being defined by a product of a pulse voltage and a pulse width, and
• said programming circuit applies in said second programming mode a second program pulse to second memory cells included in said first memory cells and having threshold voltages lower than a second reference voltage that is higher than said first reference voltage until said verifying circuit confirms that said threshold voltages of said second memory cells become higher than or equal to said second reference voltage, a programming capability of said second program pulse being lower than or equal to a programming capability of a final program pulse that is said first program pulse applied last in said first programming mode.

A nonvolatile semiconductor memory device comprising:

• a memory cell programmed by successive programming steps;
• a programming circuit applying a program pulse to said memory cell in respective of said programming steps;
• and
• a verifying circuit determining whether a programming result with respect to said memory cell to which said program pulse is applied passes or fails,
• wherein said programming-circuit includes a pulse generator,
• said pulse generator generates said program pulse with increasing a programming capability every programming step in a first programming stage, and generates said program pulse with keeping a programming capability in a second programming stage following said first programming stage constant, said programming capability being defined by a product of a pulse voltage and a pulse width, and
• said verifying circuit determines whether said programming result passes or fails based on a first reference voltage in said first programming stage and based on a second reference voltage that is higher than said first reference voltage in said second programming stage.