Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorsTakeshi Sugahara, Yukihiro Fujimoto
Life of this patent
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Abstract
A semiconductor memory device includes first and second bit lines, memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively, a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data, a hold circuit configured to maintain a potential level of the first and second bit lines, a read circuit connected to the first bit line, and a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground. The leak circuit allows a current to leak from the second bit line.
Claims11
A semiconductor memory device comprising:
- a first bit line and a second bit line;
- memory cells each including first and second storage nodes, which are connected through selecting transistors to the first and second bit lines, respectively;
- a pre-charge circuit configured to pre-charge the first and second bit lines to a predetermined potential so as to read data;
- a hold circuit configured to maintain a potential level of the first and second bit lines;
- a read circuit connected to the first bit line;
- and
- a leak circuit having one terminal connected to the second bit line and another terminal connected to a ground, said leak circuit allowing a current to leak from the second bit line.
Dependencies are inferred from the claim text.