US 7,116,571 B2 · Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit has nonvolatile memory and a logic circuit which uses information stored in the nonvolatile memory to perform logical operation. The nonvolatile memory comprises bit lines, word lines, and memory cells. The memory cell comprises MOS transistors whose gate electrodes are connected with a word line. Information storage is carried out according to whether one source/drain electrode of the MOS transistors is connected with a source line or floated. During other periods than a predetermined period in the operation of accessing the memory cell, the potential difference between the source/drain electrodes of the MOS transistors constituting the memory cell is zeroed. Subthreshold leakage current is prevented from passing through the memory cell on standby. During the predetermined period in accessing operation, a potential difference is produced between the source/drain electrodes of the MOS transistors. Therefore, the bit line potential can be varied by word line selection.

Claims13

Dependent claims

A data processing circuit having a nonvolatile memory and a central processing circuit structured on one semiconductor substrate,

wherein said nonvolatile memory is capable of storing a program and/or date,
wherein said central processing circuit is capable of fetching said program from said nonvolatile memory,
wherein said nonvolatile memory comprises bit lines, word lines, and memory cells,
wherein said memory cell comprises a MOS transistor whose gate electrode is connected with a word line, and information storage is carried out according to whether one source/drain electrode of said MOS transistor is connected with a current path or floated, and
wherein a control circuit is provided which produces a potential difference between the source/drain electrodes of said MOS transistor during a predetermined period in the operation of accessing said memory cell, and makes zero the potential difference between the source/drain electrodes of said MOS transistor during periods other than said predetermined period.

2 more elements

A data processing circuit having a nonvolatile memory and a central processing circuit structured on one semiconductor substrate,

wherein said nonvolatile memory is capable of storing a program and/or data, and comprises memory cells, word lines, complementary bit lines, and differential amplifiers connected with said complementary bit lines,
wherein said central processing circuit is capable of fetching said program from said nonvolatile memory,
wherein said memory cell comprises a pair of MOS transistors whose gate electrodes are connected with the same word line;
one source/drain electrode of each of said pair of MOS transistors is separately connected with a corresponding bit line of the pair of complementary bit lines, the other source/drain electrode of one of said pair of MOS transistors is connected with a voltage signal line supplied with predetermined voltage, and the other source/drain electrodes of the other of said pair of MOS transistors is floated
wherein said memory cell is capable of storing data in accordance with said voltage signal line being connected with the other source/drain electrode of said one of said pair of MOS transistors, and
wherein during a predetermined period in the operation of accessing said memory cell, voltage is applied to said voltage signal line which voltage produces a potential difference between the voltage signal line and said bit line, and during the other periods than said predetermined period, voltage is applied which makes zero the potential difference between the voltage signal line and said bit line.

3 more elements

Dependencies are inferred from the claim text.

Semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit

Life of this patent

Abstract

Claims13