Access circuit and method for allowing external test voltage to be applied to isolated wells

A computer system, comprising:

• a processor having a processor bus;
• an input device coupled to the processor through the processor bus to allow data to be entered into the computer system;
• an out put device coupled to the processor through the processor bus to allow data to be output from the computer system;
• a data storage device coupled to the processor through the processor bus to allow data to be read from a mass storage device;
• a memory controller coupled to the processor through the processor bus;
• and a memory device coupled to the memory controller, the memory device comprising:
• a row address circuit operable to receive and decode row address signals applied to external address terminal of the memory device;
• a column address circuit operable to receive and decode column address signals applied to the external address terminal;
• a plurality of memory cell arrays each operable to store data written to or read from the array at a location determined by the decoded row address signals and the decoded column address signals, each of the memory cell arrays being fabricated in a respective array well formed in a semiconductor substrate and isolated from each other;
• a data path circuit operable to couple data signals corresponding to the data between each of the arrays and external data terminals of the memory device;
• a command decoder operable to decode a plurality of command signals applied to respective external command terminals of the memory device, the command decoder being operable to generate control signals corresponding to the decoded command signals;
• a plurality of access circuits each of which selectively couples a predetermined one of the external terminals to a respective one of the array wells, each of the access circuits comprising:
• a first transistor fabricated in a first well formed in the semiconductor substrate that is isolated from the array wells, the first transistor having a first source-drain region fabricated in the first well and being coupled to the predetermined external terminal and to the first well, a second source-drain region fabricated in the first well, and a gate electrode fabricated between the first and second source-drain regions of the first transistor and coupled to receive a first select signal for the respective array well, the first transistor being fabricated in the first well in a manner that causes a first diode to be formed between the source and drain regions of the first transistor;
• a second transistor fabricated in a second well formed in the semiconductor substrate that is isolated from the array wells, the second transistor having a first source-drain region fabricated in the second well and being coupled to the second source-drain region of the first transistor, a second source-drain region fabricated in the second well and being coupled to the second well and to a respective one of the array wells, and a gate electrode fabricated between the first and second source-drain regions of the second transistor and coupled to receive a second select signal for the respective array well, the second transistor being fabricated in the second well in a manner that causes a second diode to be formed between the source and drain regions of the second transistor, the second diode being coupled to the first diode in a back-to-back configuration;
• a first control circuit for applying the first select signal to the gate electrode of the first transistor responsive to a first access signal;
• and
• a second control circuit for applying the second select signal to the gate electrode of the second transistor responsive to a second access signal.