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US 7,116,504 B1Granted
DC-offset compensation loops for magnetic recording system
AssigneeMarvell International Ltd.
InventorMats Oberg
Life of this patent
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Abstract
An apparatus, method, and system for providing dc offset reduction in a communications channel include two or more feedback loops to generate dc offset correction signals, which in turn are combined with an input analog signal and a processed digital signal thereby reducing dc offset. Each feedback loop may include an adaptive filter. At least one feedback loop may be responsive to an error signal that represents the difference between the delayed input of a first detector, and its output. Further, the dc offset correction signal, partially delayed, may be added to the error signal, thereby improving the response time of the dc offset correction loop.
Claims159
An apparatus for removing dc offset from a digital signal, the apparatus comprising:
- a first detector responsive to a corrected digital signal, wherein the first detector provides a first output comprising binary signals and a second output comprising a substantially error free detector input;
- a circuit to produce an error signal, wherein the error signal is the difference between the second output and the sum of an uncorrected digital signal and a dc offset correction signal, wherein the uncorrected digital signal is delayed by a first amount, and wherein the dc offset correction signal is delayed by a second amount;
- a first dc offset correction feedback loop responsive to a first loop input, the first dc offset correction feedback loop further comprising a first loop filter;
- and
- a second dc offset correction feedback loop responsive to a second loop input and a third loop input, the second dc offset correction feedback loop further comprising a second loop filter;
- wherein the first loop input is the error signal,
- wherein the second loop input is the error signal,
- wherein the third loop input is one of the corrected digital signal, the uncorrected digital signal, the first output, or the second output,
- wherein a dc offset correction signal is the sum of the output of the first dc offset correction feedback loop and at least a portion of the output of the second dc offset correction feedback loop, and
- wherein the dc offset correction signal is added to the digital signal to provide the corrected digital signal.
7 more elements
An apparatus for removing dc offset from a digital signal, the apparatus comprising:
- a first detector means responsive to a corrected digital signal, wherein the first detector provides a first output comprising binary signals and a second output comprising a substantially error free detector input;
- a means to produce an error signal, wherein the error signal is the difference between the second output and the sum of an uncorrected digital signal and a dc offset correction signal, wherein the uncorrected digital signal is delayed by a first amount, and wherein the dc offset correction signal is delayed by a second amount;
- a first feedback means responsive to a first loop input, the first feedback means further comprising a first loop filtering means;
- a second feedback means responsive to a second loop input and a third loop input, the second feedback means further comprising a second loop filtering means;
- and
- wherein the first loop input is the error signal,
- wherein the second loop input is the error signal,
- wherein the third loop input is one of the corrected digital signal, the uncorrected digital signal, the first output, or the second output,
- wherein a dc offset correction signal is the sum of the output of the first feedback means and of at least a portion of the output of the second feedback means, and
- wherein the dc offset correction signal is added to the digital signal to provide the corrected digital signal.
7 more elements
A method for removing dc offset from a digital signal, the method comprising:
- processing a corrected digital signal to provide a first output comprising binary signals and a second output comprising a substantially error free detector input;
- generating an error signal by subtracting the sum of an uncorrected digital signal and a dc offset correction signal from the second output, wherein the uncorrected digital signal is delayed by a first amount, and wherein the sum of the delayed uncorrected digital signal and the dc offset correction signal is delayed by a second amount;
- generating the digital dc offset signal by adding the output of a first dc offset correction feedback loop and at least a portion of the output of a second dc offset correction feedback loop, wherein the output of the first dc offset correction feedback loop is responsive to a first loop input, and wherein the output of the second dc offset correction feedback loop is responsive to a second loop input and a third loop input;
- and
- adding the digital dc offset signal to the digital signal thereby removing dc offset from the digital signal and generating the corrected digital signal,
- wherein the first loop input is the error signal,
- wherein the second loop input is the error signal, and
- wherein the third loop input is one of the corrected digital signal, the uncorrected digital signal, the first output, or the second output.
5 more elements
Dependencies are inferred from the claim text.