Display apparatus and controlling method thereof

A display apparatus, comprising:

• an input interface part for receiving a video signal;
• a chip including a first circuit part for receiving a digital video signal from the input interface part and for outputting first RGB digital signals and at least one of horizontal and vertical synchronous signals of the digital video signal, a second circuit part for receiving an analog video signal from the input interface part, for converting the analog video signal into second RGB digital signals, and for outputting the second RGB digital signals and a phase-locked ioop (PLL) clock signal, and a third circuit part connected to said first and second circuit parts for receiving and processing the first and second RGB digital signals, said at least one of the horizontal and vertical synchronous signals of the digital video signal, and the PLL clock signal;
• and
• a controller for detecting said at least one of the horizontal and vertical synchronous signals of the digital video signal, for setting a power saving mode when said at least one of the horizontal and vertical synchronous signals of the digital video signal is not detected, and for lowering a clock frequency of the chip when the power saving mode is set when said at least one of the horizontal and vertical synchronous signals of the digital video signal is not detected.

A display apparatus, comprising:

• input means for receiving analog and digital video signals outputted from a video card;
• a plurality of driving components;
• a scaler chip including a first circuit and a second circuit for processing the analog video signals and the digital video signals, respectively, and a third circuit having inputs connected to respective outputs of said first and second circuits;
• and
• a controller connected to said third circuit for detecting horizontal and vertical synchronous signals, and for establishing a power saving mode when at least one of the horizontal and vertical synchronous signals is not detected;
• wherein said first circuit receives and processes the analog video signals and horizontal and vertical synchronous signals of the analog video signals to produce a first RGB digital output and a phase-locked loop (PLL) clock signal;
• wherein said second circuit receives and processes the digital video signals to produce a second RGB output and horizontal and vertical synchronous signals of the digital video signals;
• wherein said third circuit processes the first and second RGB outputs, the PLL clock signal, and the horizontal and vertical synchronous signals of the digital video signals;
• and
• said controller turns off the driving components and lowers a number of driving clocks according to establishment of a power saving mode when at least one of the horizontal and vertical synchronous signals of the analog video signals is not detected.