Voltage- and temperature-compensated RC oscillator circuit

An integrated voltage-compensated and temperature-compensated RC oscillator circuit including:

• an inverter having an input and an output;
• a resistor having a first terminal and a second terminal, the first terminal coupled to the output of the inverter;
• a capacitor coupled between the second terminal of the resistor and a fixed potential;
• a first analog comparator having an inverting input, a non-inverting input coupled to the second terminal of the resistor, and an output;
• a second analog comparator having an inverting input coupled to the second terminal of the resistor, a non-inverting input, and an output;
• a voltage-divider network including a first resistor connected between a power-supply potential and a first node, a second resistor connected between the first node and a second node, and a third resistor connected between the third node and ground, the first node coupled to the inverting input of the first analog comparator and the second node coupled to the non-inverting input of the second analog comparator;
• a set-reset flip-flop having a set input coupled to the output of the first analog comparator, a reset input coupled to the output of the second analog comparator, and an output coupled to the input of the inverter;
• the first and second analog comparators comprising differential amplifiers each having a diode-connected MOS transistor in series with an inverting-input MOS transistor and a mirrored MOS transistor in series with a non-inverting-input transistor, the inverting-input and non-inverting-input input transistors having equal channel widths and the diode-connected current mirror transistor having a width larger than the width of the mirrored MOS transistor, the differential amplifier further having a MOS bias transistor having a drain coupled to the sources of the inverting-input and non-inverting-input n-channel input transistors, a source coupled to ground, and a gate coupled to a bias-voltage supply.

A temperature-compensated analog comparator including:

• a diode-connected p-channel MOS transistor having a source coupled to a power-supply potential, and a gate and drain coupled together;
• an inverting-input n-channel MOS transistor having a drain coupled to the drain of the diode-connected p-channel MOS transistor, a gate coupled to an inverting input node, and a source;
• a mirrored p-channel MOS transistor having a source coupled to the power-supply potential, a gate coupled to the gate of the diode-connected p-channel MOS transistor, and a drain;
• a non-inverting-input n-channel transistor having a drain coupled to the drain of the mirrored p-channel MOS transistor, a gate coupled to a non-inverting input node, and a source coupled to the source of the inverting-input n-channel MOS transistor;
• an n-channel MOS bias transistor having a drain coupled to the sources of the inverting and non-inverting input n-channel MOS transistors, a source coupled to ground, and a gate coupled to a bias voltage node;
• wherein the inverting-input and non-inverting-input n-channel input transistors have equal channel widths and the diode-connected p-channel MOS transistor has a width larger than the width of the mirrored p-channel MOS transistor.

A temperature-compensated analog comparator including:

• a diode-connected n-channel MOS transistor having a source coupled to a power-supply potential, and a gate and drain coupled together;
• an inverting-input p-channel MOS transistor having a drain coupled to the drain of the diode-connected p-channel MOS transistor, a gate coupled to an inverting input node, and a source;
• a mirrored n-channel MOS transistor having a source coupled to the power-supply potential, a gate coupled to the gate of the diode-connected p-channel MOS transistor, and a drain;
• a non-inverting-input p-channel transistor having a drain coupled to the drain of the mirrored p-channel MOS transistor, a gate coupled to a non-inverting input node, and a source coupled to the source of the inverting-input p-channel MOS transistor;
• a p-channel MOS bias transistor having a drain coupled to the sources of the inverting and non-inverting input p-channel MOS transistors, a source coupled to ground, and a gate coupled to a bias voltage node;
• wherein the inverting-input and non-inverting-input p-channel input transistors have equal channel widths and the diode-connected n-channel MOS transistor has a width larger than the width of the mirrored n-channel MOS transistor.