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US 7,116,176 B2Granted
Multiple synthesized clocks from a single clock source
AssigneeBroadcom Corporation
InventorsSiavash Fallahi, Chun Ying Chen, Mark J. Chambers
Life of this patent
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Abstract
A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.
Claims26
A method of generating multiple synthesized clocks, the method comprising:
- receiving a reference signal;
- generating a plurality of signals that are frequency locked to the reference signal and that have a plurality of different phases;
- assigning a relative weighting to the plurality of signals to form a plurality of weighted signals;
- and
- combining the weighted signals to form a first output signal, wherein the relative weighting determines an output phase of the first output signal.
2 more elements
A system comprising:
- a phase locked loop circuit configured to generate a plurality of signals that are frequency locked to a reference signal and that have a plurality of different phases;
- and
- a phase rotator coupled to the phase locked loop circuit to provide an output signal having a phase based on the plurality of signals.
Dependencies are inferred from the claim text.