High-swing folded cascode having a novel gain-boost amplifier

An operational amplifier, comprising:

• an input stage that is arranged to provide a first current to a first node and a second current to a second node in response to a differential input signal;
• and
• a cascode stage coupled to the input stage, the cascode stage comprises,
• a first transistor coupled between a first power supply and a first node, wherein the first transistor is biased by a first bias voltage,
• a second transistor coupled between the first power supply and a second node, wherein the second transistor is biased by the first bias voltage,
• a third transistor coupled between the first node and a third node,
• a first high-side gain boost amplifier coupled between the first node and a fifth node that couples to receive a second bias voltage, wherein the third transistor is biased by the first high-side gain boost amplifier, the first high-side gain boost amplifier, comprises,
• a first input transistor coupled between the first power supply rail and a first amplifier node, wherein the first input transistor is biased by the first node,
• a second input transistor coupled between the first power supply rail and a second amplifier node, wherein the first input transistor is biased by the fifth node,
• a current mirror coupled between the first and second amplifier nodes, the current mirror comprises a first high-side transistor and a second high-side transistor, the first high-side transistor coupled between the first amplifier node and a third amplifier node, the second high-side transistor coupled between the second amplifier node and a fourth amplifier node, the third amplifier node coupled to bias the first high-side transistor and the second high-side transistor,
• a first current source coupled between the third amplifier node and the second power supply rail,
• a second current source coupled between the fourth amplifier node and the second power supply rail,
• a third high-side transistor coupled between a fifth amplifier node and the second power supply rail, wherein the third high-side transistor is biased by the fourth amplifier node, and
• a third current source coupled between the first power supply rail and the fifth amplifier node, wherein the fifth amplifier node is an output of the first high-side gain boost amplifier,
• a fourth transistor coupled between the second node and a fourth node,
• a second high-side gain boost amplifier coupled between the second node and the fifth node that couples to receive the second bias voltage, wherein the fourth transistor is biased by the second high-side gain boost amplifier,
• a common-mode feedback circuit coupled between the third and fourth nodes to provide a common-mode feedback bias signal,
• a fifth transistor coupled between the third node and a seventh node,
• a first low-side gain boost amplifier coupled between the seventh node and a sixth node that couples to receive a third bias voltage, wherein the fifth transistor is biased by the first low-side gain boost amplifier,
• a sixth transistor coupled between the fourth node and an eighth node,
• a second low-side gain boost amplifier coupled between the eighth node and the sixth node that couples to receive the third bias voltage, wherein the sixth transistor is biased by the second low-side gain boost amplifier,
• a seventh transistor coupled between the seventh node and a second power supply, wherein the seventh transistor is biased by a fourth bias voltage, and
• a eighth transistor coupled between the eighth node and the second power supply, wherein the eighth transistor is biased by the fourth bias voltage.