Low power charge pump

A charge pump electronic circuit for boosting a low input voltage, wherein inputs of said charge pump electronic circuit comprise a first driving signal and a second driving signal, wherein said first and second driving signals are outputs of a first clock signal generation circuit, wherein inputs of said first clock signal generation circuit are a third clock signal and a fourth clock signal, said charge pump electronic circuit for boosting comprising:

• a first threshold voltage cancellation pass gate device coupled with a low input voltage source providing the low input voltage;
• a first pump node coupled with said first threshold voltage cancellation pass gate device and a first capacitive element;
• a first pump driving node coupled with said first capacitive element for receiving said first driving signal;
• a second pump node coupled with a second capacitive element;
• a second pump driving node coupled with said second capacitive element for receiving said second driving signal, wherein said second driving signal is 180 degrees out of phase with said first driving signal;
• a pump driving node pre-charge pass gate device for selectively coupling said first pump driving node to said second pump driving node, wherein when said first and second driving signals are in concurrent high impedance states, said pump driving node pre-charge pass gate device transfers charge from said first pump driving node to said second pump driving node;
• a second threshold voltage cancellation pass gate device for coupling said first pump node with said second pump node;
• a coupling between said first pump node and said second threshold voltage cancellation pass gate device;
• a fifth signal coupled with said second threshold voltage cancellation pass gate device for increasing voltage at said second threshold voltage cancellation pass gate device above a voltage of said first pump node, wherein said fifth signal is a boosted version of said third clock signal;
• and
• a sixth signal coupled with said first threshold voltage cancellation pass gate device for increasing voltage at said first threshold voltage cancellation pass gate device above a voltage of said low input voltage source, wherein said sixth signal is a boosted version of said fourth clock signal.