Stress tolerant high voltage back-to-back switch
AssigneeIntel Corporation
InventorsGerald J. Barkley, Daniel J. Chu
Life of this patent
Estimating the term…
Abstract
Methods and apparatuses associated with stepping down a high voltage in a high voltage switch. An additional transistor may be coupled to a switching transistor, and the additional transistor biased to a voltage level in between the high voltage to be switched and a switch reference voltage. When the switch is off, the high voltage may thus be spread across multiple devices to prevent a voltage from the gate to the drain to exceed a threshold associated with gate-aided breakdown of the drain-to-substrate channel-side pn-junction.
Claims22
A circuit for voltage switching in an integrated circuit, comprising:
- a first p-type transistor having a source, a gate, a drain, and a substrate, the substrate coupled with the source, the source coupled with a high voltage potential line to receive a voltage potential that is higher than a gate-to-drain pn-junction breakdown voltage associated with the first transistor, and the gate coupled with a line to have a voltage potential substantially equal to the high voltage;
- a second p-type transistor having a source, a gate, a drain, and a substrate, the substrate coupled with the source, the source coupled with a low voltage potential line, the low voltage controlled to be lower than the high voltage, the gate coupled with a control signal line, and the drain to have a voltage potential substantially equal to the low voltage, the difference between the high voltage and the voltage on the drain equal to or higher than the breakdown voltage;
- and
- a third p-type transistor having a source, a gate, a drain, and a substrate, the substrate coupled with the source of the first transistor, the source coupled with the drain of the first transistor, the drain coupled with the drain of the second transistor, and the gate coupled with a bias signal line to have a voltage potential between the high voltage and the voltage on the drain of the second transistor.
A device to supply a voltage to a circuit, comprising:
- a switching circuit having a p-type voltage switching transistor with a source and a gate coupled in an off condition to a high voltage, a difference in potential between the high voltage and a reference voltage exceeding a drain-substrate inner pn-j unction breakdown voltage of the transistor;
- an additional p-type transistor with a drain coupled to a drain of the switching transistor, the drain of the additional p-type transistor being driven to the reference voltage;
- and
- a voltage stepping transistor coupled between the drain of the switching transistor and the drain of the additional transistor, a gate of the stepping transistor to be biased in the off condition of the switching transistor to an intermediate voltage between the high voltage and the reference voltage, to prevent the reference voltage on drain of the additional transistor from being on the drain of the switching transistor;
- and
- a biasing circuit coupled with the switching circuit to provide the bias voltage to the gate of the voltage stepping transistor.
A method for switching voltage, comprising:
- supplying a voltage level to the source of a switching p-type transistor that is greater than a gate-aided reverse breakdown voltage of a drain-to-channel-substrate junction characteristic of the transistor, and supplying the voltage level to the gate of the switching transistor to generate an off condition;
- supplying a low voltage level to the source of an additional p-type transistor in a back-to-back configuration with the switching transistor, and driving the drain to the low voltage;
- and
- biasing the gate of a third p-type transistor when the off condition is generated to turn the third transistor on, the third p-type transistor to couple the drain of the switching transistor with the drain of the additional transistor.
A system comprising:
- a switching circuit having
- a p-type voltage switching transistor with a source and a gate coupled in an off condition to a high voltage, a difference in potential between the high voltage and a reference voltage exceeding a drain-substrate inner pn-junction breakdown voltage;
- an additional p-type transistor with a drain coupled to a drain of the switching transistor, the drain of the additional p-type transistor being driven to the reference voltage;
- and
- a voltage stepping transistor coupled between the drain of the switching transistor and the drain of the additional transistor, a gate of the stepping transistor to be biased in the off condition of the switching transistor to an intermediate voltage between the high voltage and the reference voltage, to prevent the reference voltage on drain of the additional transistor from being on the drain of the switching transistor;
- and
- a memory array coupled with the switch to selectively be passed the high voltage through the switch.
Dependencies are inferred from the claim text.