Clock gater circuit and associated method
AssigneeHewlett-Packard Development Company, L.P.
InventorErin Dean Francom
Life of this patent
Estimating the term…
Abstract
One embodiment is a clock gater circuit comprising an inverter block for driving an output clock signal responsive at least in part to an input clock signal that is selectively driven via a clock generator circuit to an input node of the inverter block responsive to a qualifier signal. Also included is circuitry for restoring a logic level at the input node of the inverter block to a particular value, the circuitry operating responsive to the qualifier signal.
Claims17
A clock gater circuit, comprising:
- an inverter block for driving an output clock signal responsive at least in part to an input clock signal that is selectively driven via a clock generator circuit to an input node of said inverter block responsive to a qualifier signal, wherein said inverter block comprises a pair of cross-coupled inverters;
- and
- circuitry for restoring a logic level at said input node of said inverter block to a particular value, said circuitry operating responsive to said qualifier signal.
A clock gater circuit, comprising:
- clock generator means for selectively driving a clock signal to an input node of an inverter block, said clock generator means operating responsive to a qualifier signal, wherein said inverter block drives an output clock signal responsive to said clock signal at said input node, said inverter block including a pair of cross-coupled inverters;
- and
- means for restoring a logic level at said input node of said inverter block to a particular value, said means operating responsive to said qualifier signal.
A method of generating a clock signal using a clock gater circuit, comprising:
- driving an input clock signal via a clock generator circuit portion of said clock gater circuit for generating an output clock signal, said driving being selectively controlled by a qualifier signal;
- and
- maintaining a voltage level of said output clock signal at a current voltage thereof by a pull-up structure operating responsive to said qualifier signal, said pull-up structure including a first transistor and a second transistor coupled together in series such that said first transistor's gate is driven by said output clock signal and said second transistor's gate is driven by said qualifier signal.
Dependencies are inferred from the claim text.