Circuit and method for interpolative delay

A circuit comprising a delay locked loop (DLL) with interpolation delay, the DLL comprising:

• a differential inverter coupled to receive a differential clock signal and coupled to provide an inverted differential clock signal;
• an interpolation circuit coupled to receive both the clock signal and the inverted clock signal, and to provide an interpolated clock signal having a first delay relative to the clock signal;
• and
• a differential compare circuit coupled to receive the inverted clock signal and coupled to provide a non-interpolated clock signal having a second delay relative to the clock signal, wherein the second delay corresponds to a full delay of the differential inverter and the first delay corresponds to a predetermined fraction of the full delay.

A method for providing clock signals comprising:

• providing a differential clock signal to a delay circuit, the delay circuit including a plurality of series-coupled delay stages, each delay stage delaying the clock signal by a delay unit and inverting the clock signal;
• providing a plurality of differential delay stage output signals;
• providing, for each differential delay stage output signal, a single-ended clock signal;
• interpolating between pairs of the differential delay stage clock signals;
• providing, for each delay stage, an interpolated single-ended clock signal.

A circuit comprising:

• first circuit means for summing a first signal and a second signal;
• second circuit means for summing a third signal and a fourth signal;
• and
• third circuit means for comparing the sum of the first and second signals and the sum of the third and fourth signals;
• wherein the first and third signals are complementary signals of a first differential signal, the second and fourth signals are complementary signals of a second differential signal, and the second differential signal is a delayed inversion of the first differential signal;
• a differential inverter coupled to receive the first and third signals and to provide the second and fourth signals;
• a plurality of differential inverters including the differential inverter;
• a plurality of interpolative comparison circuits, each interpolative comparison circuit corresponding to a differential inverter and including a corresponding instance of the first, second and third circuit means, each interpolative comparison circuit being coupled to receive corresponding first, second, third and fourth signals.