Phase-locked loop circuit having phase lock detection function and method for detecting phase lock thereof

A phase-locked loop circuit, comprising:

• a phase-frequency detector configured to generate an up signal and a down signal that indicate the phase difference between a reference signal and a feedback signal;
• a charge pump configured to receive the up signal and the down signal from the phase-frequency detector to output a dc voltage signal in response to a state of the up signal or the down signal;
• a loop filter configured to integrate the output signal of the charge pump to generate an integrated signal;
• a voltage-controlled oscillator configured to receive the integrated signal from the loop filter to generate an oscillating signal whose frequency is controlled in accordance with a dc level of the integrated signal;
• a lock-detection-start-signal generator configured to receive the up signal and the down signal generated by the phase-frequency detector to generate a delay time and to further generate a lock detection start signal when a pulse width of the up signal or the down signal is less than the delay time;
• a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal, a duration of which is determined by rising edges of the up signal and the down signal;
• and
• a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator and count the lock detection clock to generate a lock detection signal.

A lock detection method of a phase-locked loop circuit, comprising:

• receiving an up signal and a down signal generated on the basis of a phase difference between a reference signal and a feedback signal, thereby generating a delay time and further generating a lock detection start signal when a pulse width of the up signal and down signal is less than the delay time;
• generating a lock detection clock signal, a duration of which is determined by rising edges of the up signal and down signal;
• and
• receiving the lock detection start signal and the lock detection clock signal to count the number of the lock detection clock signals, thereby generating a lock detection signal.

A phase-locked loop circuit, comprising:

• a phase-frequency detector configured to generate an up signal and a down signal that indicate the phase difference between a reference signal and a feedback signal;
• a charge pump configured to receive the up signal and the down signal from the phase-frequency detector to output a dc voltage signal in response to a state of the up signal or the down signal;
• a loop filter configured to integrate the output signal of the charge pump to generate an integrated signal;
• a voltage-controlled oscillator configured to receive the integrated signal from the loop filter to generate an oscillating signal whose frequency is controlled in accordance with a dc level of the integrated signal;
• and
• a lock detection circuit configured to receive the up signal and the down signal to generate a lock detection signal indicating the lock state of phase, wherein the lock detection signal is generated in a third operating region when an operating region of the phase-locked loop circuit is divided into three parts, a first operating region where the input voltage of the voltage-controlled oscillator increases continuously, a second operating region where an amplitude of the input voltage is decreased while the input voltage of the voltage-controlled oscillator is repeatedly increased and decreased in rotation and the up signal and the down signal are generated alternately, and the third operating region where the input voltage of the voltage-controlled oscillator is converged to a certain value and maintains the value, wherein the lock detection circuit comprises at least one latch circuit that receives the up signal and down signal and latches the up signal and the down signal to detect whether the up signal and the down signal are generated alternately.

A lock detection method of a phase-locked loop circuit, comprising:

• generating an up signal and a down signal indicating the phase difference between a reference signal and a feedback signal
• receiving the up signal and the down signal to output a dc voltage signal corresponding to the state of the up signal and the down signal;
• integrating the dc voltage signal to generate an integrated signal;
• generating an oscillating signal whose frequency changes in accordance with the dc level of the integrated signal;
• and
• receiving the up and down signals to generate a lock detection signal indicating the lock state of phase, wherein the lock detection signal is generated in a third operating region when an operating region of the phase-locked loop circuit is divided into three parts, a first operating region where the input voltage of the voltage-controlled oscillator increases continuously, a second operating region where an amplitude of the input voltage is decreased while the input voltage of the voltage-controlled oscillator is repeatedly increased and decreased in rotation and and the up signal and the down signal are generated alternately, and wherein the up signal and the down signal are latched to detect whether the up signal and the down signal are generated alternately, and a third operating region where the input voltage of the voltage-controlled oscillator is converged to a value and maintains the value.

A lock detection circuit in a phase-locked loop circuit including a phase-frequency detector and a voltage-controlled oscillator, comprising:

• a lock-detection-start-signal generator configured to receive an up signal and a down signal generated by the phase-frequency detector, to generate a lock detection start signal when a pulse width of the up signal or the down signal reaches a predetermined value;
• a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal on the basis of the up signal and the down signal, wherein the lock-detection-clock generator comprises:
• a first latch circuit configured to receive the up signal and the down signal and latch the signals to output a first output signal and a second output signal;
• and
• a second latch circuit configured to receive the first output signal and the second output signal and latch the signals to generate the lock detection clock signal;
• and
• a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator, and count the lock detection clock, to generate a lock detection signal indicative of a lock state in the phase-locked loop circuit.

A lock detection circuit in a phase-locked loop circuit including a phase-frequency detector and a voltage-controlled oscillator, comprising:

• a lock-detection-start-signal generator configured to receive an up signal and a down signal generated by the phase-frequency detector, to generate a lock detection start signal when a pulse width of the up signal or the down signal reaches a predetermined value;
• a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal on the basis of the up signal and the down signal;
• and
• a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator, and count the lock detection clock, to generate a lock detection signal indicative of a lock state in the phase-locked loop circuit, wherein the lock-detection-signal generator includes at least one flip-flop connected in cascade that is controlled by the lock detection clock signal, and wherein each of the flip-flops is cleared by the lock detection start signal.

A lock detection circuit in a phase-locked loop circuit including a phase-frequency detector and a voltage-controlled oscillator, comprising:

• a lock-detection-start-signal generator configured to receive an up signal and a down signal generated by the phase-frequency detector, to generate a lock detection start signal when a pulse width of the up signal or the down signal reaches a predetermined value;
• a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal on the basis of the up signal and the down signal;
• and
• a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator, and count the lock detection clock, to generate a lock detection signal indicative of a lock state in the phase-locked loop circuit, wherein the lock-detection-signal generator includes at least one flip-flop connected in cascade that is controlled by the lock detection clock signal, wherein an input terminal of the first flip-flop receives a signal of logic “1”, and each of input terminals of the flip-flops following after the first stage flip-flop receives an output signal of the preceding stage flip-flop, and wherein the lock-detection-start-signal generator is cleared by a reset signal, and the signal of logic “1” is an inverted signal of the reset signal.

A phase-locked loop circuit, comprising:

• a phase-frequency detector configured to generate an up signal and a down signal that indicate the phase difference between a reference signal and a feedback signal;
• a charge pump configured to receive the up signal and the down signal from the phase-frequency detector to output a dc voltage signal in response to a state of the up signal or the down signal;
• a loop filter configured to integrate the output signal of the charge pump to generate an integrated signal;
• a voltage-controlled oscillator configured to receive the integrated signal from the loop filter to generate an oscillating signal whose frequency is controlled in accordance with a dc level of the integrated signal;
• a lock-detection-start-signal generator configured to receive the up signal and the down signal generated by the phase-frequency detector to generate a lock detection start signal when the pulse width of the up signal and the down signal reaches a predetermined value;
• a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal on the basis of the up signal and the down signal, wherein the lock-detection-clock generator comprises:
• a first latch circuit configured to receive the up signal and the down signal and latch the signals, to output a first output signal and a second output signal;
• and
• a second latch circuit configured to receive the first output signal and the second output signal and latch the signals to generate the lock detection clock signal;
• and
• a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator and count the lock detection clock to generate the lock detection signal.

A phase-locked loop circuit, comprising:

• a phase-frequency detector configured to generate an up signal and a down signal that indicate the phase difference between a reference signal and a feedback signal;
• a charge pump configured to receive the up signal and the down signal from the phase-frequency detector to output a dc voltage signal in response to a state of the up signal or the down signal;
• a loop filter configured to integrate the output signal of the charge pump to generate an integrated signal;
• a voltage-controlled oscillator configured to receive the integrated signal from the loop filter to generate an oscillating signal whose frequency is controlled in accordance with a dc level of the integrated signal;
• a lock-detection-start-signal generator configured to receive the up signal and the down signal generated by the phase-frequency detector to generate a lock detection start signal when the pulse width of the up signal and the down signal reaches a predetermined value;
• a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal on the basis of the up signal and the down signal;
• and
• a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator and count the lock detection clock to generate the lock detection signal, wherein the lock-detection-signal generator includes at least one flip-flop connected in cascade that is controlled by the lock detection clock signal, wherein each of the flip-flops is cleared by the lock detection start signal.

A phase-locked loop circuit, comprising:

• a phase-frequency detector configured to generate an up signal and a down signal that indicate the phase difference between a reference signal and a feedback signal;
• a charge pump configured to receive the up signal and the down signal from the phase-frequency detector to output a dc voltage signal in response to a state of the up signal or the down signal;
• a loop filter configured to integrate the output signal of the charge pump to generate an integrated signal;
• a voltage-controlled oscillator configured to receive the integrated signal from the loop filter to generate an oscillating signal whose frequency is controlled in accordance with a dc level of the integrated signal;
• a lock-detection-start-signal generator configured to receive the up signal and the down signal generated by the phase-frequency detector to generate a lock detection start signal when the pulse width of the up signal and the down signal reaches a predetermined value;
• a lock-detection-clock generator configured to receive the up signal and the down signal to generate a lock detection clock signal on the basis of the up signal and the down signal;
• and
• a lock-detection-signal generator configured to receive the lock detection start signal from the lock-detection-start-signal generator and the lock detection clock signal from the lock-detection-clock generator and count the lock detection clock to generate the lock detection signal, wherein the lock-detection-signal generator includes at least one flip-flop connected in cascade that is controlled by the lock detection clock signal, wherein an input terminal of the first flip-flop receives a signal of logic “1”, and each of the input terminals of the flip-flops succeeding after the first stage flip-flop receives an output signal of the preceding stage flip-flop, and wherein the lock-detection-start-signal generator is cleared by a reset signal, and the signal of logic “1” is an inverted signal of the reset signal.

A lock detection method of a phase-locked loop circuit, comprising:

• receiving an up signal and a down signal generated on the basis of a phase difference between a reference signal and a feedback signal, thereby generating a lock detection start signal when the pulse width of the up signal and down signal reaches a predetermined value;
• generating a lock detection clock signal on the basis of the up signal and down signal, wherein generating the lock detection clock signal comprises:
• receiving and latching the up signal and the down signal to output a first output signal and a second output signal;
• and
• receiving and latching the first output signal and the second output signal to output the lock detection clock signal;
• and
• receiving the lock detection start signal and the lock detection clock signal to count the number of the lock detection clock signals, thereby generating the lock detection signal.