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US 7,116,143 B2Granted
Synchronous clock generator including duty cycle correction
AssigneeMicron Technology, Inc.
InventorsVinoth Kumar Deivasigamani, Tyler Gomm
Life of this patent
Estimating the term…
Abstract
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle. The clock generator includes an input buffer to buffer the input clock signal and generate a buffered clock signal and an output buffer to generate the output clock signal in response to first and second clock signals applied to first and second inputs. An adjustable delay loop coupled to the output of the input buffer and coupled to the first and second inputs of the output buffer has a single feedback delay loop and is configured to generate a first clock signal and a second clock signal. The second clock signal is out of phase from the first clock signal by 180 degrees.
Claims48
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the fixed delay circuit configured to generate a delayed clock signal having a fixed delay relative to the full-delayed clock signal;
- and
- an adjustable delay circuit controller coupled to the adjustable delay circuit and the output of the input buffer, the adjustable delay circuit controller configured to adjust the adjustable delay to provide a forward delay equal to an odd multiple of a period of the input clock signal, the forward delay including an input buffer delay of the input buffer, the adjustable delay, the first fixed delay, and an output buffer delay of the output buffer.
3 more elements
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a first fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the first fixed delay circuit configured to generate a delayed clock signal having a first fixed delay relative to the full-delayed clock signal;
- a second fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output, the second fixed delay circuit configured to generate a feedback clock signal having a second fixed delay relative to the full-delayed clock signal that is equal to twice the first delay;
- and
- a phase detector having a first input coupled to the output of the input buffer, a second input coupled to the output of the second fixed delay circuit, and an output coupled to the control node of the adjustable delay circuit, the phase detector configured to generate the delay adjustment signal to adjust the adjustable delay according to the relative phase of the buffered clock signal and the feedback clock signal.
4 more elements
A clock generator for generating an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a first fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the first fixed delay circuit configured to generate a delayed clock signal having a first fixed delay relative to the full-delayed clock signal;
- a second fixed delay circuit having an input coupled to the output of the first fixed delay and further having an output, the second fixed delay circuit configured to generate a feedback clock signal having a second fixed delay relative to the full-delayed clock signal that is equal to first delay;
- and
- a phase detector having a first input coupled to the output of the input buffer, a second input coupled to the output of the second fixed delay circuit , and an output coupled to the control node of the adjustable delay circuit, the phase detector configured to generate the delay adjustment signal to adjust the adjustable delay according to the relative phase of the buffered clock signal and the feedback clock signal.
4 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- a clock generator coupled to the control circuit, the clock generator configured to generate an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the fixed delay circuit configured to generate a delayed clock signal having a fixed delay relative to the full-delayed clock signal;
- and
- an adjustable delay circuit controller coupled to the adjustable delay circuit and the output of the input buffer, the adjustable delay circuit controller configured to adjust the adjustable delay to provide a forward delay equal to an odd multiple of a period of the input clock signal, the forward delay including an input buffer delay of the input buffer, the adjustable delay, the first fixed delay, and an output buffer delay of the output buffer.
12 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- a clock generator coupled to the control circuit, the clock generator configured to generate an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a first fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the first fixed delay circuit configured to generate a delayed clock signal having a first fixed delay relative to the full-delayed clock signal;
- a second fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output, the second fixed delay circuit configured to generate a feedback clock signal having a second fixed delay relative to the full-delayed clock signal that is equal to twice the first delay;
- and
- a phase detector having a first input coupled to the output of the input buffer, a second input coupled to the output of the second fixed delay circuit, and an output coupled to the control node of the adjustable delay circuit, the phase detector configured to generate the delay adjustment signal to adjust the adjustable delay according to the relative phase of the buffered clock signal and the feedback clock signal.
13 more elements
A memory device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- a clock generator coupled to the control circuit, the clock generator configured to generate an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a first fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the first fixed delay circuit configured to generate a delayed clock signal having a first fixed delay relative to the full-delayed clock signal;
- a second fixed delay circuit having an input coupled to the output of the first fixed delay and further having an output, the second fixed delay circuit configured to generate a feedback clock signal having a second fixed delay relative to the full-delayed clock signal that is equal to first delay;
- and
- a phase detector having a first input coupled to the output of the input buffer, a second input coupled to the output of the second fixed delay circuit , and an output coupled to the control node of the adjustable delay circuit, the phase detector configured to generate the delay adjustment signal to adjust the adjustable delay according to the relative phase of the buffered clock signal and the feedback clock signal.
13 more elements
A computer processing system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- a clock generator coupled to the control circuit, the clock generator configured to generate an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the fixed delay circuit configured to generate a delayed clock signal having a fixed delay relative to the full-delayed clock signal;
- and
- an adjustable delay circuit controller coupled to the adjustable delay circuit and the output of the input buffer, the adjustable delay circuit controller configured to adjust the adjustable delay to provide a forward delay equal to an odd multiple of a period of the input clock signal, the forward delay including an input buffer delay of the input buffer, the adjustable delay, the first fixed delay, and an output buffer delay of the output buffer.
17 more elements
A computer processing system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising, an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- a clock generator coupled to the control circuit, the clock generator configured to generate an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a first fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the first fixed delay circuit configured to generate a delayed clock signal having a first fixed delay relative to the full-delayed clock signal;
- a second fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output, the second fixed delay circuit configured to generate a feedback clock signal having a second fixed delay relative to the full-delayed clock signal that is equal to twice the first delay;
- and
- a phase detector having a first input coupled to the output of the input buffer, a second input coupled to the output of the second fixed delay circuit, and an output coupled to the control node of the adjustable delay circuit, the phase detector configured to generate the delay adjustment signal to adjust the adjustable delay according to the relative phase of the buffered clock signal and the feedback clock signal.
17 more elements
A computer processing system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a memory device coupled to the processor, the memory device comprising,
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- a control circuit coupled to the control bus;
- a memory-cell array coupled to the address decoder, control circuit, and read/write circuit;
- and
- a clock generator coupled to the control circuit, the clock generator configured to generate an output clock signal synchronized with an input clock signal and having a corrected duty cycle, the clock generator comprising:
- an input buffer having an input to which the input clock is coupled and an output, the input buffer configured to buffer the input clock signal and generate a buffered clock signal;
- an output buffer having first and second inputs and further having an output at which the output clock signal is provided, the output buffer configured to generate the output clock signal in response to clock signals applied to the first and second inputs;
- an adjustable delay circuit having an input coupled to the output of the input buffer, an output, and a control node, and further having a half-delay tap coupled to the first input of the output buffer, the adjustable delay circuit configured to generate a full-delayed clock signal having an adjustable delay relative to the buffered clock signal according to an delay adjustment signal applied to the control node and further generate a half-delayed clock signal having one-half the adjustable delay relative to the buffered clock signal, the full-delay clock signal provided at the output of the adjustable delay and the half-delayed clock signal provided at the half-delay tap;
- a first fixed delay circuit having an input coupled to the output of the adjustable delay circuit and further having an output coupled to the second input of the output buffer, the first fixed delay circuit configured to generate a delayed clock signal having a first fixed delay relative to the full-delayed clock signal;
- a second fixed delay circuit having an input coupled to the output of the first fixed delay and further having an output, the second fixed delay circuit configured to generate a feedback clock signal having a second fixed delay relative to the full-delayed clock signal that is equal to first delay;
- and
- a phase detector having a first input coupled to the output of the input buffer, a second input coupled to the output of the second fixed delay circuit , and an output coupled to the control node of the adjustable delay circuit, the phase detector configured to generate the delay adjustment signal to adjust the adjustable delay according to the relative phase of the buffered clock signal and the feedback clock signal.
18 more elements
A method for generating a delayed clock signal synchronized with a reference clock signal and having a corrected duty cycle, the method comprising:
- delaying the reference clock signal by a total delay equal to an odd multiple of a period of the reference clock signal, the total delay including an input buffer delay, an adjustable delay, a fixed delay, and an output buffer delay;
- generating a first clock signal having a first delay relative to the reference clock signal equal to the input buffer delay and half of the adjustable delay;
- generating a second clock signal having a second delay relative to the reference clock signal equal to the input buffer delay, the adjustable delay, and the fixed delay;
- and
- in a time equal to the output buffer delay, combining the first clock signal and a second clock signal to provide the delayed clock signal.
2 more elements
Dependencies are inferred from the claim text.