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US 7,116,141 B2Granted
Frequency-doubling delay locked loop
AssigneeMosaid Technologies Incorporated
InventorPaul W. Demone
Life of this patent
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Abstract
A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.
Claims10
A frequency multiplier for generating an output clock signal in response to a reference input clock signal, said multiplier comprising:
- a) a delay line for receiving and delaying the reference input clock signal, said delay line having a plurality of serially coupled delay stages each having a delay stage tap output;
- b) a plurality of combining circuit cells, each cell having inputs respectively coupled to ones of a predetermined number of said delay stage tap outputs, each cell providing at least one combining cell output signal having a multiplied frequency of the reference input clock signal, said combining cell output signals from said plurality of combining circuit cells being spaced in phase;
- and
- c) a selector coupled to said combining cell outputs for selecting one of said combining cell output signals for producing the output clock signal.
1 more element
Dependencies are inferred from the claim text.