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US 7,116,137 B2Granted
Method and system for reducing power consumption in digital circuitry using charge redistribution circuits
AssigneeSTMicroelectronics Pvt. Ltd.
InventorsVivek Nautiyal, Ashish Kumar
Life of this patent
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Abstract
A method and system for reducing power consumption in digital circuits using charge redistribution include a plurality of signal lines, an intermediate floating virtual source/sink, and a charge redistribution circuit connected to each signal line that isolates the signal line from its source and connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state. This charge redistribution provides steady state statistical independent advantage due to charge recycling without inserting extra complimentary lines.
Claims20
A system for reducing power consumption in digital circuits using charge redistribution, comprising:
- a plurality of signal lines;
- an intermediate floating virtual source/sink, and
- a charge redistribution circuit connected to a source and a load portion of at least one of said signal lines that isolates the load portion of said line from its source by entering a high impedance state and that connects it to the intermediate floating virtual source/sink during an idle period prior to a change of state,
- wherein the charge redistribution circuit comprises a transition detector connected to the source of one of the signal lines and having two outputs, a first of the outputs connected to an input of a tri-state driver circuit, a second of the outputs for simultaneously (i) enabling the tri-state driver circuit to enter the high impedance state and (ii) enabling a control switch to connect an output of the tri-state driver circuit to the floating virtual source/sink whenever a transition is detected on the signal line, the output of the tri-state driver circuit coupled to the load portion of the signal line, and
- wherein the transition detector comprises a delay circuit having its input connected to the source of the signal line and its output connected to the first output of the transition detector and to a first input of a 2-input exclusive-OR or exclusive-NOR gate while a second input of the gate is directly connected to the source of the signal line and its output is connected to the second output of the transition detector.
2 more elements
An integrated circuit for reducing power consumption in digital circuits using charge redistribution, comprising:
- a plurality of signal lines;
- an intermediate floating virtual source/sink, and
- a charge redistribution circuit connected to a source and a load portion of at least one of said signal lines that isolates the load portion of said line from its source by entering a high impedance state and that connects it to the intermediate floating virtual source/sink during an idle period prior to a change of states,
- wherein the charge redistribution circuit comprises a transition detector connected to the source of one of the signal lines and having two outputs, a first of the outputs connected to an input of a tri-state driver circuit, a second of the outputs for simultaneously (i) enabling the tri-state driver circuit to enter the high impedance state and (ii) enabling a control switch to connect an output of the tri-state driver circuit to the floating virtual source/sink whenever a transition is detected on the signal line, the output of the tri-state driver circuit coupled to the load portion of the signal line, and
- wherein the transition detector comprises a delay circuit having its input connected to the source of the signal line and its output connected to the first output of the transition detector and to a first input of a 2-input exclusive-OR or exclusive-NOR gate while a second input of the gate is directly connected to the source of the signal line and its output is connected to the second output of the transition detector.
2 more elements
A method for reducing power consumption in digital circuits using charge redistribution, comprising the steps of:
- providing a plurality of signal lines;
- providing an intermediate floating virtual source/sink, and
- isolating a load portion of at least one of said signal lines from its source by (i) placing a charge redistribution circuit connected to the source and the load portion of one of the signal lines in a high impedance state and (ii) connecting the load portion of the signal line to the intermediate floating virtual source/sink during an idle period prior to a change of states,
- wherein the charge redistribution circuit comprises a transition detector connected to the source of one of the signal lines and having two outputs, a first of the outputs connected to an input of a tri-state driver circuit, a second of the outputs for simultaneously (i) enabling the tri-state driver circuit to enter the high impedance state and (ii) enabling a control switch to connect an output of the tri-state driver circuit to the floating virtual source/sink whenever a transition is detected on the signal line, the output of the tri-state driver circuit coupled to the load portion of the signal line, and
- wherein the transition detector comprises a delay circuit having its input connected to the source of the signal line and its output connected to the first output of the transition detector and to a first input of a 2-input exclusive-OR or exclusive-NOR gate while a second input of the gate is directly connected to the source of the signal line and its output is connected to the second output of the transition detector.
2 more elements
Dependencies are inferred from the claim text.