Apparatus and method for adjusting clock skew

A synchronous memory device comprising:

• an array of memory cells;
• a clock input for receiving a clock signal;
• and
• a clock input buffer comprising:
• a first and second input buffer circuit for receiving a first and second external clock signal, respectively, each of said input buffer circuits comprising:
• an input for receiving an external clock signal;
• a differential amplifier coupled to the input, said differential amplifier having an output terminal for providing a latch signal in response to the external clock signal, the latch signal having a first or second state;
• a first inverter connected to said output terminal, said first inverter generating an internal clock signal in response to the latch signal, said first inverter generating a first internal clock signal when the latch signal is in a first state, and a second internal clock signal when the latch signal is in a second state;
• and
• a circuit for reducing skew between the first and second internal clock signals, said circuit comprising:
• first and second clock signal input/output lines for receiving and transmitting first and second internal clock signals, respectively;
• and
• at least second and third inverters each having an input and an output, said input of said second inverter connected to said output of said third inverter and to said first clock signal input/output line and said input of said third inverter connected to said output of said second inverter and to said second clock signal input/output line.

A computer system comprising:

• a processor;
• and
• a memory circuit connected to said processor, said memory circuit comprising:
• an array of memory cells;
• a clock input for receiving a clock signal;
• and
• a clock input buffer comprising:
• a first and second input buffer circuit for receiving a first and second external clock signal, respectively, each of said input buffer circuits comprising:
• an input for receiving an external clock signal;
• a differential amplifier coupled to the input, said differential amplifier having an output terminal for providing a latch signal in response to the external clock signal, the latch signal having a first or second state;
• a first inverter connected to said output terminal, said first inverter generating an internal clock signal in response to the latch signal, said first inverter generating a first internal clock signal when the latch signal is in a first state, and a second internal clock signal when the latch signal is in a second state;
• and
• a circuit for reducing skew between the first and second internal clock signals, said circuit comprising:
• first and second clock signal input/output lines for receiving and transmitting first and second internal clock signals, respectively;
• and
• at least second and third inverters each having an input and an output, said input of said second inverter connected to said output of said third inverter and to said first clock signal input/output line and said input of said third inverter connected to said output of said second inverter and to said second clock signal input/output line.

A method of generating an internal clock signal in an integrated circuit, the method comprising the steps of:

• receiving first and second external clock signals, wherein the second external clock signal is an inverse of the first external clock signal and where there exists a time lag of one of said external clock signals relative to the other;
• buffering each of the first and second external clock signals using a reference voltage;
• and
• modifying the transition of one of said buffered external clock signals relative to the other to produce from said buffered external clock signals internal clock signals which have reduced skew.