Method and apparatus for effectively re-downloading data to a field programmable gate array
AssigneeBenq Corporation
InventorsFang-Bin Liu, Wu-Han Yang
Life of this patent
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Abstract
A method for effectively re-downloading data to a Field Programmable Gate Array (FPGA). The method uses two Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit, such that according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, a write-to-NVRAM operation for data is determined if the detection state is logic low and conversely data is written from the NVRAM to the FPGA.
Claims10
A method for re-downloading data to a Field Programmable Gate Array (FPGA), characterized by use of Complex Programmable Logic Devices (CPLDs) to implement control functions of Write-to-Non-Volatile Random Access Memory (NVRAM) and Write-to-FPGA respectively, in conjunction with a set of connectors with a detection circuit to determine if the CPLDs use the set of connectors to download data according to a detection state output by the detection circuit to one CPLD implemented with Write-to-FPGA control function, wherein a write-to-NVRAM operation for data is determined when the detection state is a first logic level and data is written from the NVRAM to the FPGA when the detection state is a second logic level.
An apparatus for re-downloading data to a Field Programmable Gate Array (FPGA), comprising:
- a Non-Volatile Random Access Memory (NVRAM);
- a first control block, having a first Complex Programmable Logic Device (CPLD) implementing a control function of receiving and writing a reconfiguration data code to the NVRAM;
- a first connector with a first detection circuit, connected to the first control block to receive the reconfiguration data code;
- a second control block, having a second CPLD implementing a control function of reading the reconfiguration data code from the NVRAM and writing the reconfiguration data code to an FPGA;
- and
- a second connector with a second detection circuit, connected to the second control block to transfer a detection state to the second control block, the second connector optionally connected to or disconnected from the first connector,
- wherein when the first connector and the second connector are separate, the detection state presents a first potential such that the second control block reads the reconfiguration data code stored in the NVRAM and writes the reconfiguration data code into an FPGA;
- when the first connector and the second connector are connected to connect the first detection circuit and the second detection circuit, the detection state presents a second-potential such that the first control block writes the reconfiguration data code into the NVRAM.
Dependencies are inferred from the claim text.