Temperature-compensated output buffer method and circuit

An output buffer, comprising:

• a pull-up circuit, including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor, the supplemental pull-up circuit configured to generate, in response to a supplemental pull-up control signal, a supplemental pull-up output signal, the first pull-up output signal and the supplemental pull-up output signal coupled to form a pull-up output signal, wherein the supplemental pull-up circuit is configured to generate the supplemental pull-up output signal in response to the pull-up input signal and the supplemental pull-up control signal and wherein the supplemental pull-up circuit comprises a second pull-up transistor configured in parallel with the first pull-up transistor, the second pull-up transistor controlled in part by each of the pull-up input signal and the supplemental pull-up control signal;
• and
• a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal responsive to a pull-down input signal, and a supplemental pull-down circuit in parallel with the first pull-down transistor, the supplemental pull-down circuit configured to generate, in response to a supplemental pull-down control signal, a supplemental pull-down output signal, the first pull-down output signal and the supplemental pull-down output signal coupled to form a pull-down output signal, the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal.

An output buffer, comprising:

• a pull-up circuit, including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor, the supplemental pull-up circuit configured to generate, in response to a supplemental pull-up control signal, a supplemental pull-up output signal, the first pull-up output signal and the supplemental pull-up output signal coupled to form a pull-up output signal;
• a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal responsive to a pull-down input signal, and a supplemental pull-down circuit in parallel with the first pull-down transistor, the supplemental pull-down circuit configured to generate, in response to a supplemental pull-down control signal, a supplemental pull-down output signal, the first pull-down output signal and the supplemental pull-down output signal coupled to form a pull-down output signal, the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal;
• and
• wherein the supplemental pull-down circuit is configured to generate the supplemental pull-down output signal in response to the pull-down input signal and the supplemental pull-down control signal and wherein the supplemental pull-down circuit comprises a second pull-down transistor configured in parallel with the first pull-down transistor, the second pull-down transistor controlled in part by each of the pull-down input signal and the supplemental pull-down control signal.

An output buffer, comprising:

• a pull-up circuit, including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor, the supplemental pull-up circuit configured to generate, in response to a supplemental pull-up control signal, a supplemental pull-up output signal, the first pull-up output signal and the supplemental pull-up output signal coupled to form a pull-up output signal;
• a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal responsive to a pull-down input signal, and a supplemental pull-down circuit in parallel with the first pull-down transistor, the supplemental pull-down circuit configured to generate, in response to a supplemental pull-down control signal, a supplemental pull-down output signal, the first pull-down output signal and the supplemental pull-down output signal coupled to form a pull-down output signal, the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal;
• and
• a biasing circuit for generating the pull-up control signal and the pull-down control signal for respectively controlling the supplemental pull-up circuit and the supplemental pull-down circuit, wherein the biasing circuit is configured to generate the pull-up control signal as complementary to absolute temperature (CTAT).

An output buffer, comprising:

• a pull-up circuit, including a first pull-up transistor for providing a first pull-up output signal responsive to a pull-up input signal, and a supplemental pull-up circuit in parallel with the first pull-up transistor, the supplemental pull-up circuit configured to generate, in response to a supplemental pull-up control signal, a supplemental pull-up output signal, the first pull-up output signal and the supplemental pull-up output signal coupled to form a pull-up output signal;
• a pull-down circuit, including a first pull-down transistor for providing a first pull-down output signal responsive to a pull-down input signal, and a supplemental pull-down circuit in parallel with the first pull-down transistor, the supplemental pull-down circuit configured to generate, in response to a supplemental pull-down control signal, a supplemental pull-down output signal, the first pull-down output signal and the supplemental pull-down output signal coupled to form a pull-down output signal, the pull-up output signal and the pull-down output signal coupled to form an output buffer output signal;
• and
• a biasing circuit for generating the pull-up control signal and the pull-down control signal for respectively controlling the supplemental pull-up circuit and the supplemental pull-down circuit, wherein the biasing circuit is configured to generate the pull-down control signal as proportional to absolute temperature (PTAT).

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with temperature variation;
• and
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation.

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with over a temperature variation;
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation;
• and
• a biasing circuit for generating the pull-up control signal and the pull-down control signal for respectively controlling the supplemental pull-up circuit and the supplemental pull-down circuit, wherein the biasing circuit is configured to generate the pull-up control signal as complementary to absolute temperature (CTAT).

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with over a temperature variation;
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation;
• and
• a biasing circuit for generating the pull-up control signal and the pull-down control signal for respectively controlling the supplemental pull-up circuit and the supplemental pull-down circuit, wherein the biasing circuit is configured to generate the pull-down control signal as proportional to absolute temperature (PTAT).

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with over a temperature variation, wherein the supplemental pull-up circuit comprises a second pull-up transistor configured in parallel with the first pull-up transistor, the second pull-up transistor controlled in part by each of the pull-up input signal and the supplemental pull-up control signal;
• and
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation.

A memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with over a temperature variation;
• and
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation, wherein the supplemental pull-down circuit comprises a second pull-down transistor configured in parallel with the first pull-down transistor, the second pull-down transistor controlled in part by each of the pull-down input signal and the supplemental pull-down control signal.

A semiconductor substrate on which is fabricated a semiconductor memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with temperature variation;
• and
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation.

A semiconductor substrate on which is fabricated a semiconductor memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with over a temperature variation, wherein the supplemental pull-up circuit comprises a second pull-up transistor configured in parallel with the first pull-up transistor, the second pull-up transistor controlled in part by each of the pull-up input signal and the supplemental pull-up control signal;
• and
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation.

A semiconductor substrate on which is fabricated a semiconductor memory device, comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with over a temperature variation;
• and
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation, wherein the supplemental pull-down circuit comprises a second pull-down transistor configured in parallel with the first pull-down transistor, the second pull-down transistor controlled in part by each of the pull-down input signal and the supplemental pull-down control signal.

A method of providing a data output signal, comprising:

• generating a first pull-up output signal in response to a first pull-up input signal;
• generating a supplemental pull-up output signal responsive to a supplemental pull-up control signal, the supplemental pull-up control signal varying with temperature variations;
• generating a first pull-down output signal in response to a first pull-down input signal;
• generating a supplemental pull-down output signal responsive to a supplemental pull-down control signal, the supplemental pull-down control signal varying with the temperature variations;
• and
• combining the first pull-up output signal and the supplemental pull-up output signal to form a pull-up output signal and the first pull-down output signal and the supplemental pull-down output signal to form a pull-down output signal.

An electronic system comprising an input device, an output device, a memory device, and a processor device coupled to the input, output, and memory devices, at least one of the input, output, memory, and processor devices including a semiconductor memory comprising:

• an array of memory cells;
• a plurality of data lines for access to the array of memory cells;
• and
• an output buffer coupled between the array of memory cells and the plurality of data lines, the output buffer including at least one output buffer circuit, comprising:
• a supplemental pull-up circuit configured in parallel with a first pull-up transistor, the supplemental pull-up circuit responsive to both a pull-up input signal and a supplemental pull-up control signal variable with temperature variation;
• and
• a supplemental pull-down circuit configured in parallel with a first pull-down transistor, the supplemental pull-down circuit responsive to both a pull-down input signal and a supplemental pull-down control signal variable over the temperature variation.