CPU surge reduction and protection

A computer system comprising:

• a power supply;
• and
• a circuit, the circuit including a power output stage, a voltage regulator coupled to the power output stage, and a processor coupled to a surge notification input of the power output stage, the power output stage to receive a system voltage of the power supply and having an output node to receive a processor voltage of the power supply, the voltage regulator to selectively switch the power output stage into a current ramp down mode based on a voltage surge at the output node, the power output stage having an associated current ramp down rate, the power output stage to accelerate the current ramp down rate based on a notification signal from the processor.

A method of protecting a processor from voltage surges, comprising:

• switching a power output stage into a current ramp down mode based on a voltage surge at an output node of the power output stage, the power output stage having an associated current ramp down rate;
• and
• accelerating the current ramp down rate based on a surge notification signal from the processor.

A power circuit comprising:

• a power output stage, the power output stage including a transistor stack, an output inductor and a transient adjustment circuit, the transistor stack having a switching node, the output inductor defining a ramp down current path and having a first terminal coupled to the switching node and a second terminal coupled to an output node of the power output stage;
• a voltage regulator coupled to the power output stage, the voltage regulator including a metal oxide semiconductor field effect transistor (MOSFET) driver, a comparator and a reference component, the MOSFET driver coupled to the transistor stack of the power output stage, the comparator having a first input coupled to the output node and a comparator output coupled to the MOSFET driver, the reference component to apply a reference voltage to a second input of the comparator;
• a processor coupled to the output node and having a surge notification output coupled to a surge notification input of the transient adjustment circuit, the transient adjustment circuit to reduce an effective inductance of the ramp down current path in response to a surge notification signal from the processor, the notification signal to correspond to a gating off of unused portions of the processor.