Seedless wirebond pad plating
AssigneeInternational Business Machines Corporation
InventorsChandrasekhar Narayan, Kevin Shawn Petrarca
Life of this patent
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Abstract
An integrated circuit (IC) chip, semiconductor wafer with IC chips in a number of die locations and a method of making the IC chips on the wafer. The IC chips have plated chip interconnect pads. Each plated pad includes a noble metal plated layer electroplated to a platable metal layer. The platable metal layer may be copper and the noble metal plated layer may be of gold, platinum, palladium, rhodium, ruthenium, osmium, iridium or indium.
Claims21
An integrated circuit (IC) chip with circuits formed thereon, a plurality of chip interconnect pads formed on a surface of said IC chip, one or more of said plurality of chip interconnect pads being an electroplated pad, said electroplated pad having a plated layer plated to a platable pad, said plated pad including an electrical connection to an underlying strap, said underlying strap extending horizontally from said electrical connection to a chip side wall.
A semiconductor wafer with a plurality of die locations, each of said die locations being separated from other said die locations by a kerf space, said semiconductor wafer comprising:
- a plurality of integrated circuit (IC) chips, each IC chip including a plurality of devices formed on semiconductor surface of said semiconductor wafer in one of said die locations, said devices being wired together into a circuit, selected ones of said devices being connected to one of a plurality of chip pads;
- a conductive grid line in each said kerf space;
- a conductive ring, each said conductive grid line being connected to said conductive ring;
- and
- a conductive strap connected to one of said plurality of chip pads on said each chip, each of said plurality of chip pads being connected to one said conductive strap, each said conductive strap being connected to an adjacent said conductive grid line, whereby a bias supply current provided to said conductive ring, passes through to each of said plurality of chip pads on said each chip.
Dependencies are inferred from the claim text.