Back to results
US 7,115,994 B2Granted
Semiconductor substrate and method of fabricating semiconductor device
AssigneeFujitsu Limited
InventorTetsuo Yaegashi
Life of this patent
Estimating the term…
Abstract
A semiconductor substrate includes a wafer including an element area and a non-element area delineating the element area, a first layered structure situated in the element area, a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe, a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate, and a second layered structure situated in the non-element area, wherein the second layered structure includes at least a portion of the first layered structure.
Claims11
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area defining the element area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate;
- and
- a second layered structure situated in the non-element area;
- wherein the second layered structure is formed from one or more of the same materials as the first layered structure.
4 more elements
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area delineating the element, area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching-recipe, the second etching rate being greater than the first etching rate;
- a second layered structure situated in the non-element area;
- wherein the second layered structure includes at least a portion of the first layered structure;
- wherein the second insulating film includes a first aperture portion penetrating the first insulating film in a manner exposing the first layered structure, a first conductive pattern disposed in the first aperture portion, a second aperture portion exposing the second layered structure, and a second conductive pattern disposed in the second aperture portion.
4 more elements
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area delineating the element, area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching-recipe, the second etching rate being greater than the first etching rate;
- a second layered structure situated in the non-element area;
- wherein the second layered structure includes at least a portion of the first layered structure;
- wherein the second layered structure has a same layer structure as the first layered structure.
4 more elements
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area delineating the element, area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching-recipe, the second etching rate being greater than the first etching rate;
- a second layered structure situated in the non-element area;
- wherein the second layered structure includes at least a portion of the first layered structure;
- wherein the second layered structure is formed as a first alignment mark, wherein the second layered structure has a second alignment mark formed in correspondence with the first alignment mark.
4 more elements
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area delineating the element, area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching-recipe, the second etching rate being greater than the first etching rate;
- a second layered structure situated in the non-element area;
- wherein the second layered structure includes at least a portion of the first layered structure;
- wherein the first insulating film is a film for preventing hydrogen from entering the etching recipe.
4 more elements
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area delineating the element, area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching-recipe, the second etching rate being greater than the first etching rate;
- a second layered structure situated in the non-element area;
- wherein the second layered structure includes at least a portion of the first layered structure;
- wherein the first insulating film contains Al2O3.
4 more elements
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area delineating the element, area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching-recipe, the second etching rate being greater than the first etching rate;
- a second layered structure situated in the non-element area;
- wherein the second layered structure includes at least a portion of the first layered structure;
- wherein the first layered structure is a capacitor structure including a lower electrode, a ferroelectric film situated on the lower electrode, and an upper electrode situated on the upper electrode.
4 more elements
A semiconductor substrate comprising:
- a wafer including an element area and a non-element area delineating the element, area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching-recipe, the second etching rate being greater than the first etching rate;
- a second layered structure situated in the non-element area;
- wherein the second layered structure includes at least a portion of the first layered structure;
- wherein the non-element area is a scribe line formed on the wafer for delineating the element area.
4 more elements
A semiconductor device comprising:
- a wafer including an element area and a non-element area defining the element area;
- a first layered structure situated in the element area;
- a first insulating film covering the first layered structure, and exhibiting a first etching rate with respect to an etching recipe;
- a second insulating film covering the first layered structure covered by the first insulating film in the element area, and exhibiting a second etching rate with respect to the etching recipe, the second etching rate being greater than the first etching rate;
- and
- a second layered structure situated in the non-element area;
- wherein the second layered structure is formed from one or more of the same materials as the first layered structure.
4 more elements
Dependencies are inferred from the claim text.