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US 7,115,992 B2Granted
Electrode structure for use in an integrated circuit
AssigneeMicron Technology, Inc.
InventorsJohn T. Moore, Joseph F. Brooks
Life of this patent
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AssigneeMicron Technology, Inc.
InventorsJohn T. Moore, Joseph F. Brooks
Estimating the term…
An electrode structure includes a first layer of conductive material and a dielectric layer formed on a surface of the first layer. An opening is formed in the dielectric layer to expose a portion of the surface of the first layer. A binding layer is formed on the dielectric layer and on the exposed portion of the surface of the first layer and a second layer of conductive material is formed on the conductive binding layer. The binding layer can be an oxide and the second layer a conductive material that is diffusible into an oxide. The electrode structure can be annealed to cause conductive material from the second layer to be chemisorbed into the binding layer to improve adhesion between the first and second layers. A programmable cell can be formed by forming a doped glass layer in the electrode structure.
An electrode structure, comprising:
A memory cell, comprising:
A memory cell, comprising:
A memory cell, comprising:
A memory cell, comprising:
A memory cell, comprising:
A memory cell, comprising:
A memory system, comprising:
A memory system, comprising:
A memory system, comprising:
A memory system, comprising:
A memory system, comprising:
A memory system, comprising:
An electronic system, comprising:
An electronic system, comprising:
An electronic system, comprising:
An electronic system, comprising:
An electronic system, comprising:
An electronic system, comprising:
A memory cell, comprising:
A memory system, comprising:
An electronic system, comprising:
A memory cell, comprising:
A memory system, comprising:
An electronic system, comprising:
Dependencies are inferred from the claim text.
From the US filing history. Foreign family members aren’t listed.
RRAM elements whose operation depends upon chemical change: comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
Modification of switching materials after formation, e.g. doping: by diffusion, e.g. photo-dissolution
Shaping switching materials: by filling of openings, e.g. damascene method
Based on migration or redistribution of ionic species, e.g. anions, vacancies: the species being metal cations, e.g. programmable metallization cells
Term ended 12 May 2022 (estimated)
The present invention relates generally to semiconductor chips and integrated circuits, and more particularly to an electrode structure for use in integrated circuits, such as electronic systems, memory systems and the like.
In fabricating integrated circuits, semiconductor chips and the like, chemical/mechanical planarization can be used as an intermediate operation to planarize a structure to provide a uniform, level surface for subsequent processing operations in the manufacturing of a semiconductor chip or integrated circuit. For example, electrodes or electrical contacts between different layers of conductive materials in a semiconductor chip can be formed by depositing a first layer of conductive material, typically a metal, although a semiconductor material could be used as well, and then depositing a thin dielectric layer over the first conductive layer. The dielectric layer is then patterned to form at least one opening in the dielectric layer to expose a portion of the surface of the first conductive layer. The opening can have a small aspect ratio of depth to width. For instance, the opening can be about half a micron wide but only about 500 angstroms deep thus presenting a aspect ratio of about 0.1. A second layer of a different conductive material is then deposited on the dielectric layer and in the opening on the first conductive layer to make electrical contact through the opening with the first conductive layer. The second conductive layer is then removed form the dielectric layer or planarized to expose the dielectric layer and to form an isolated electrode or damascene contact structure in the opening before subsequent fabrication operations. In removing the second conductive layer by chemical/mechanical processing or planarization (CMP), the forces created by the CMP process can have a tendency to force the conductive material of the second layer out of the opening thereby destroying the contact.
Accordingly, for the reason stated above, and for other reasons that will become apparent upon reading and understanding the present specification, there is a need for an electrode structure and method of fabrication that provides substantially improved adhesion between a first layer of conductive material and second layer of a different conductive material, particularly during a CMP operation, and that does not adversely effect the conductivity between the two layers or create an electrical barrier. There is also a need for a method of fabricating an electrode structure that does not effect or damage other components that may already have been formed on the same wafer or substrate and that does not adversely effect the manufacturing process by requiring a significant number of additional process operations.
In the drawings, like numerals describe substantially similar components throughout the several views. Like numerals having different letter suffixes or primed (X′) represent different occurrences of substantially similar components.
FIGS. 1A–1C illustrate the operations in forming an electrode for use in an integrated circuit in accordance with the present invention.
FIGS. 2A–D illustrate the operations in forming a programmable memory cell in accordance with an embodiment of the present invention.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments can be utilized and that process or mechanical changes may be made without departing from the scope of the present invention. The terms wafer and substrate used in the following description include any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor, as well as other semiconductor support structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process operations may have been utilized to form regions/junctions in the base semiconductor structure. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.
The transistors described herein include transistors from bipolar-junction technology (BJT), field effect technology (FET), or complimentary metal-oxide-semiconductor (CMOS) technology. A metal-oxide-semiconductor (MOS) transistor includes a gate, a first node (drain) and a second node (source). Since a MOS transistor is typically a symmetrical device, the true designation of “source” and “drain” is only possible once voltage is impressed on the terminals. The designations of source and drain herein should be interpreted, therefore, in the broadest sense. It should also be noted that a P-channel MOS transistor could alternatively be used for an N-channel MOS transistor and vice versa with the polarity of the associated gate voltages merely being reversed. For example, applying a negative gate voltage in the situation of a P-channel MOS transistor to activate the transistor and reversing the polarity to apply a positive gate voltage to activate an N-channel transistor if an N-channel MOS transistor is substituted for a P-channel transistor.
FIGS. 1A–1C illustrate the operations in forming an electrode structure 100 in accordance with the present invention. In FIG. 1A, a first layer 102 of conductive material is deposited or formed. The first layer 102 of conductive material can be tungsten, nickel or a semiconductor material. A dielectric layer 104 is formed on the first conductive layer 102. The dielectric layer 104 can be a nitride, such as silicon nitride or a similar dielectric material. The dielectric layer 104 is patterned by standard photolithographic techniques or the like to form at least one opening 106 through the dielectric layer 104 to expose a portion of a surface 108 of the first conductive layer 102. The opening 106 can have a width “W” or a diameter that is significantly larger than a depth “D” to provide a small aspect ratio; however, the invention is not limited to such aspect ratios. A layer 110 of oxide is formed on the dielectric layer 104 and on the surface 108 of the first conductive layer 102. The oxide layer 110 can be a silicon oxide deposited by the thermal reaction of a precursor, such as tetraethyl orthosilicate (TEOS) or the like. The oxide layer 110 can have a thickness between about 50 angstroms and about 200 angstroms. A second layer 112 of conductive material is formed on the oxide layer 110. The second layer 112 of conductive material can be silver, nickel or another metal or conductive material that can diffuse into the oxide layer 110 and bond to the oxide layer 110.
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