US 7,115,977 B2Granted

Multi-chip package type semiconductor device

AssigneeOki Electric Industry Co., Ltd.

InventorsMitsuru Komiyama, Shinsuke Suzuki

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Abstract

A multi-chip package type semiconductor device includes an insulating substrate having first and second conductive patterns thereon, a first semiconductor chip on the insulating substrate and having a first terminal pad and a relay pad isolated from the first terminal pad. The device further includes a second semiconductor chip on the first semiconductor chip having a second terminal pad. The first semiconductor chip is connected to the first pattern by a first bonding wire. The second semiconductor chip is connected to the second pattern by a second bonding wire, which connects the second pattern to the relay pad, and a third bonding wire, which connects the relay pad to the second terminal pad. The lengths of the first, second and third bonding wire are approximately the same.

Claims26

Dependent claims

A multi-chip package type semiconductor device, comprising:

an insulating substrate having thereon a first conductive pattern and a second conductive pattern;
a first semiconductor chip having a plurality of first internal circuits on the insulating substrate, the first semiconductor chip having a plurality of first terminal pads, each of which is connected to one of the first internal circuits and a plurality of conductive relay pads, each of which is isolated from the first terminal pads, and each of the conductive relay pads including a first area and a second area;
which is different from the first area, wherein each first terminal pad and each conductive relay pad are alternatively aligned;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip being smaller than the first semiconductor chip, and having a second internal circuit and having a second terminal pad connecting to the second internal circuit;
a plurality of first metal bumps, each of which is formed on one of the conductive relay pads in the first area;
a second metal bump formed on the second terminal pad;
a first bonding wire, wherein one end thereof is formed on one of the first terminal pads and the other end is formed on the first conductive pattern;
a second bonding wire, wherein one end thereof is formed on the second conductive pattern and the other end is formed at the top of the first metal bump on one of the conductive relay pads in the first area;
and
a third bonding wire, wherein one end thereof is formed on the one of the conductive relay pads in the second area and the other end is formed at the top of the second metal bump,
wherein the lengths of the first, second and third bonding wire are approximately the same.

8 more elements

A multi-chip package type semiconductor device, comprising:

a first semiconductor chip having a plurality of first terminal pads and a plurality of conductive relay pads, each of the conductive relay pads including a first area and a second area, which is different from the first area, wherein each first terminal pad and each conductive relay pad are alternatively aligned;
a second semiconductor chip, which is placed on the first semiconductor chip, the second semiconductor chip having a second terminal pad, connected to one of the conductive relay pads in the second area;
a plurality of first metal bumps, each of which is formed on one of the conductive relay pads in the first area;
a second metal bump formed on the second terminal pad;
a first internal terminal connected to one of the first terminal pads;
a second internal terminal connected to one of the conductive relay pads in the first area;
a first bonding wire, wherein one end thereof is formed on the first internal terminal and the other end is formed on one of the first terminal pads;
a second bonding wire, wherein one end thereof is formed on the second internal terminal and the other end is formed at the top of the first metal bump formed on one of the conductive relay pads;
and
a third bonding wire, wherein one end thereof is formed on the one of the conductively relay pads in the second area and the other end is formed at the top of the second metal bump.

7 more elements

A multi-chip package type semiconductor device, comprising:

an insulating substrate having thereon a first conductive pattern and a second conductive pattern;
a first semiconductor chip having a plurality of first internal circuits on the insulating substrate, the first semiconductor chip having a plurality of first terminal pads, each of which is connected to one of the first internal circuits and a plurality of conductive relay pads, each of which is isolated from the first terminal pads, and each of which includes a first area and a second area which is different from the first area, each first terminal pad and each conductive relay pad are alternatively aligned;
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip being smaller than the first semiconductor chip, and having a second internal circuit and having a second terminal pad connecting to the second internal circuit;
a plurality of metal bumps, each of which is formed on one of the conductive relay pads in the second area;
a first bonding wire, wherein one end thereof is formed on one of the first terminal pads and the other end is formed on the first conductive pattern;
a second bonding, wherein one end thereof is formed on the second conductive pattern and the other end is formed on one of the conductive relay pads in the first area;
and
a third bonding wire, wherein one end thereof is formed on the second terminal pad and the other end is formed at the top of the metal bump on the one of the conductive relay pads in the second area;
wherein the lengths of the first, second and third bonding wire are approximately the same.

6 more elements

Dependencies are inferred from the claim text.