US 7,115,965 B2 · Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Abstract

The present invention provides a “subcollector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped subcollector. Instead, the inventive vertical SOI BJT uses a back gate-induced, majority carrier accumulation layer as the subcollector when it operates. The SOI substrate is biased such that the accumulation layer is formed at the bottom of the first semiconductor layer. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS. A back-gated CMOS device is also provided.

Claims14

Dependent claims

A bipolar transistor comprising:

a conductive back electrode for receiving a bias voltage;
a second buried insulating layer located over said conductive back electrode having a second thickness;
a first buried insulating layer located adjacent to said second buried insulating layer and said conductive back electrode, said first buried insulating layer having a first thickness that is greater than the second thickness;
a first semiconductor layer located predominately over said second buried insulating layer, said first semiconductor layer including a first conductive type dopant, wherein said conductive back electrode is biased to form an accumulation layer in said first semiconductor layer at an interface between said first semiconductor layer and said second buried insulating layer;
a base located atop at least said first semiconductor layer, said base comprising a second semiconductor layer having a second conductivity type dopant that differs from the first conductivity type dopant;
and
an emitter comprising a third semiconductor layer of the first conductivity type dopant located over a portion of said base.

4 more elements

An integrated semiconductor structure comprising

a bipolar transistor including a conductive back electrode for receiving a bias voltage, a second buried insulating layer located over said conductive back electrode having a second thickness, a first buried insulating layer located adjacent to said second buried insulating layer and said conductive back electrode, said first buried insulating layer having a first thickness that is greater than the second thickness, a first semiconductor layer located predominately over said second buried insulating layer, said first semiconductor layer including a first conductive type dopant, wherein said conductive back electrode is biased to form an accumulation layer in said first semiconductor layer at an interface between said first semiconductor layer and said second buried insulating layer, a base located atop at least said first semiconductor layer, said base comprising a second semiconductor layer having a second conductivity type dopant that differs from the first conductivity type dopant, and an emitter comprising a third semiconductor layer of the first conductivity type dopant located over a portion of said base;
and
at least one adjacent complementary metal oxide semiconductor device.

Dependencies are inferred from the claim text.

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Life of this patent

Vertical bipolar transistor with a majority carrier accumulation layer as a subcollector for SOI BiCMOS with reduced buried oxide thickness for low-substrate bias operation

Life of this patent

Abstract

Claims14