US 7,115,957 B2Granted

Semiconductor raised source-drain structure

AssigneeMicron Technology, Inc.

InventorsFernando Gonzalez, Chandra Mouli

Life of this patent

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Abstract

A transistor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain.

Claims10

Dependent claims

A transistor formed on a substrate assembly, comprising:

a raised drain structure;
a raised source structure;
a gate located between said source and said drain, wherein a top surface of said raised drain structure, a top surface of said raised source structure, and a top surface of said gate are positioned substantially within a common plane;
a first capping layer in communication with at least a portion of said gate and said source;
a first portion of a gate oxide structure in communication with at least a portion of said gate and said source;
a first pocket implant junction located in said substrate assembly, said first pocket implant junction comprising a first high dose dopant implant and defining a first low-resistance path, wherein said first pocket implant junction is in communication with said source predominantly along a non-sidewall portion thereof and extends under a first portion of said gate;
a second capping layer in communication with at least a portion of said gate and said drain;
a second portion of said gate oxide region in communication with at least a portion of said gate and said drain;
a second pocket implant junction located in said substrate assembly, said second pocket implant junction comprising a second high dose dopant implant and defining a second low-resistance path, wherein said second pocket implant junction is in communication with said drain predominantly along a non-sidewall portion thereof and extends under a second portion of said gate;
a first field oxide region at least partially recessed within the substrate assembly and in communication with the raised drain structure;
and
a second field oxide region at least partially recessed within the substrate assembly and in communication with the raised source structure.

9 more elements

A transistor formed on a substrate assembly, comprising:

a raised drain structure;
a raised source structure;
a gate located between said source and said drain, wherein a top surface of said raised drain structure, a top surface of said raised source structure, and a top surface of said pate are positioned substantially within a common plane;
a first capping layer in communication with at least a portion of said gate and said source;
a first portion of a gate oxide region in communication with at least a portion of said gate and said source;
a first pocket implant junction located in said substrate assembly, said first pocket implant junction comprising a first high dose dopant implant and defining a first low-resistance path, wherein said first pocket implant junction is in communication with said source predominantly along a non-sidewall portion thereof and extends under a first portion of said gate;
a first outdiffusion area located in said substrate assembly and extending under at least a portion of said source;
a second capping layer in communication with at least a portion of said gate and said drain;
a second portion of said gate oxide region in communication with at least a portion of said gate and said drain;
a second pocket implant junction located in said substrate assembly;
said second pocket implant junction comprising a second high dose dopant implant and defining a second low-resistance path, wherein said second pocket implant junction is in communication with said drain predominantly along a non-sidewall portion thereof and extends under a second portion of said gate;
a second outdiffusion area located in said substrate assembly and extending under at least a portion of said drain;
a first field oxide region at least partially recessed within the substrate assembly and in communication with the raised drain structure;
and
a second field oxide region at least partially recessed within the substrate assembly and in communication with the raised source structure.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/008,653Filed 9 Nov 2001 · division
Priority: 1 Sep 1998
Published: US 2002/0043694 A118 Apr 2002
Granted: 3 Oct 2006
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/679
Gate sidewall spacers: comprising air gaps
H10D 30/0218
Of FETs having insulated gates [IGFET]: having pocket halo regions selectively formed at the sides of the gates
H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates
H10D 64/0111
Of electrodes ohmically coupled to a semiconductor: to Group IV semiconductors

Family

Application09/144,662Parent of this division · filed 1 Sep 1998
US 2002/0043694 A1Pre-grant publication · published 18 Apr 2002
US 6,693,335 B2Parent of this division
US 2001/0022381 A1Published application
US 7,115,957 B2This patent

From the US filing history. Foreign family members aren’t listed.