Transistor constructions and electronic devices

A field effect transistor construction, comprising:

• a crystalline layer separated from a substrate by an insulative material;
• the crystalline layer comprising a material which includes silicon and germanium;
• a body region within the crystalline layer, the body region including a charge trapping region which contains silicon-rich-nitride;
• an entirety of the body region within the crystalline layer being within a single crystal of the crystalline layer;
• first and second diffusion regions within the body region;
• a channel region within the body region between the first and second diffusion regions;
• and
• a gate over the channel region.

A semiconductor-on-insulator field effect transistor (SOI-FET) construction, comprising:

• an electrically insulative material;
• a first crystalline layer over the electrically insulative material;
• the first crystalline layer having a relaxed crystalline lattice;
• a second crystalline layer over the first crystalline layer;
• the second crystalline layer having a strained crystalline lattice;
• a gate over the second crystalline layer;
• a body region extending into the first and second crystalline layers proximate the gate, the body region including a pair of diffusion regions coupled with one another through the gate;
• the body region including a silicon-rich-insulator (SRI) layer;
• an entirety of the body region within the first crystalline layer being within a single crystal of the first crystalline layer;
• and
• wherein the SOI-FET has a first threshold voltage associated with a non-volatile first memory state when excess charges are trapped in the SRI layer, and a second threshold voltage associated with a second memory state when trapped charges in the SRI layer are neutralized.

An electronic device, comprising:

• a substrate;
• a memory array, including:
• a crystalline Si/Ge layer formed over the substrate;
• and
• a number of memory cells organized in a number of rows and a number of columns;
• at least some of the memory cells including transistors which comprise floating body regions extending into the crystalline Si/Ge layer and containing charge trapping regions which comprise silicon-rich-nitride;
• the at least some of the transistors including first and second diffusion regions within the body regions, and including transistor gates over the body regions;
• wherein at least one of the floating body regions extending within the crystalline Si/Ge layer is entirely contained within a single crystal of the crystalline Si/Ge layer;
• and
• control circuitry operably connected to the memory array to write selected memory cells and to read selected memory cells.

A field effect transistor construction, comprising:

• a crystalline material which includes silicon and germanium;
• a body region within the crystalline material, the body region including a charge trapping region;
• the charge trapping region comprising silicon oxynitride, transition metal oxide, metal silicide, silicon-rich-nitride or silicon-rich-oxide;
• first and second diffusion regions within the body region;
• a channel region within the body region between the first and second diffusion regions;
• and
• a gate over the channel region.