MOS transistor having an offset region

A semiconductor device comprising:

• a semiconductor region of a first conductivity type;
• an offset region of the second conductivity type, provided in a surface of the semiconductor region, the impurity dominant in the offset region being diffused to a position deeper than a position where concentration of an impurity of the first conductivity type is highest in the semiconductor region, the offset region being formed in such a manner that it has a smaller depth than the position where concentration of the impurity of the first conductivity type is highest in the semiconductor region;
• a drain region of the second conductivity type, provided in a surface of the offset region;
• a source region of the second conductivity type, provided in the surface of the semiconductor region and isolated from the offset region;
• a gate insulating film provided on that part of the semiconductor region which lies between the offset region and the source region;
• and
• a gate electrode provided on the gate insulating film, the position where the concentration of the impurity of the first conductivity type is highest in the semiconductor region being shallower than the position where the concentration of the impurity dominant in the offset region is 1/10 the highest concentration of the impurity of the first conductivity type in the semiconductor region.

A semiconductor device comprising:

• a semiconductor region of a first conductivity;
• a drain region provided in a surface of the semiconductor region;
• a source region provided in the surface of the semiconductor region and isolated from the drain region;
• an offset region provided in the surface of the semiconductor region, isolated from the source region, covering the drain region and having a first region and a second region, said first region being a surface region of the offset region and including a carrier path extending between the source region and the drain region, said second region being the remaining region of the offset region;
• a gate insulating film provided on that part of the semiconductor region which lies between the offset region and the source region;
• and
• a gate electrode provided on the gate insulating film;
• wherein the junction between the semiconductor region and the second region has an impurity concentration higher than that of the junction between the semiconductor region and the first region, and
• when a breakdown voltage at a pn junction between the offset region and the semiconductor region is applied to a junction between the source region and the drain region, breakdown occurs at a junction between the second region and the semiconductor region before breakdown occurs at the junction between the first region and the semiconductor region.

A semiconductor device comprising:

• a semiconductor region of a first conductivity type;
• a drain region of the first conductivity type, provided in a surface of the semiconductor region and shaped like a stripe;
• an offset region of the first conductivity type, provided in the surface of the semiconductor region and surrounding the drain region;
• a body region of the second conductivity type, provided in the surface of the semiconductor region and having a shape that encircles all peripheries of the offset region and the drain region on all sides in a horizontal plane of the semiconductor region;
• a source region of the first conductivity, provided in a surface of the body region and having a shape that encircles all peripheries of the offset region and the drain region on all sides in a horizontal plane of the semiconductor region;
• a gate insulating film provided on that part of the body region which lies between the offset region and the source region;
• and
• a gate electrode provided on the gate insulating film.

A semiconductor device comprising:

• a semiconductor region of a first conductivity type;
• an offset region of the second conductivity type, provided in a surface of the semiconductor region;
• a drain region of the second conductivity, provided in a surface of the offset region;
• a source region of the second conductivity type, provided in the surface of the semiconductor region and isolated from the offset region;
• a gate insulating film provided on that part of the semiconductor region which lies between the offset region and the source region;
• and
• a gate electrode provided on the gate insulating film,
• in a region where the drain region, the offset region and the semiconductor region overlap one another, the impurity dominant in the offset region being diffused to a position deeper than a position where the concentration of an impurity of the first conductivity type is highest in the semiconductor region;
• in the region where the drain region, the offset region and the semiconductor region overlap one another, the offset region being formed in such a manner that it has a smaller depth than the position where the concentration of the impurity of the first conductivity type is highest in the semiconductor region;
• and
• the position where the concentration of the impurity of the first conductivity type is highest in the semiconductor region being shallower than the position where the concentration of the impurity dominant in the offset region is 1/10 the highest concentration of the impurity of the first conductivity type in the semiconductor region.