Semiconductor memory device including multi-layer gate structure

A semiconductor memory device comprising:

• a memory cell unit including at least one memory cell transistor, the memory cell transistor including:
• first and second semiconductor regions with a first conductivity which are formed apart from each other in a surface of a semiconductor layer with a second conductivity opposite to the first conductivity;
• and
• a multi-layer gate electrode which is formed on the semiconductor layer between the first and second semiconductor regions with a first gate insulating film interposed therebetween, the multi-layer gate electrode including a charge accumulation layer and a control gate;
• a first insulating film formed on the first and second semiconductor regions;
• a select transistor which selects the memory cell unit, the select transistor including:
• third and fourth semiconductor regions with the first conductivity which are formed apart from each other in a surface of the semiconductor layer;
• and
• a first gate electrode which is formed on the semiconductor layer between the third and fourth semiconductor regions with a second gate insulating film interposed therebetween;
• a second insulating film formed on the third semiconductor region, at least a part of an interface between the third semiconductor region and second insulating film being positioned low to have a first stepped portion with respect to an interface between the semiconductor layer and second gate insulating film;
• a third insulating film formed on the fourth semiconductor region, at least a part of an interface between the fourth semiconductor region and the third insulating film being positioned low to have a second stepped portion with respect to an interface between the semiconductor layer and second gate insulating film;
• and
• a first contact plug which is formed in a region of the second stepped portion, the first contact plug being partially in contact with the second stepped portion and being electrically connected to one of bit and source lines, a part of the third insulating film being partially in contact with the second stepped portion.