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US 7,115,921 B2Granted
Nano-scaled gate structure with self-interconnect capabilities
AssigneeInternational Business Machines Corporation
InventorsLawrence A. Clevenger, Timothy Joseph Dalton, Louis L. Hsu, Carl Radens, Keith Kwong Hon Wong, Chih-Chao Yang
Life of this patent
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Abstract
Gate conductors on an integrated circuit are formed with enlarged upper portions which are utilized to electrically connect the gate conductors with other devices. A semiconductor device comprises a gate conductor with an enlarged upper portion which electrically connects the gate conductor to a local diffusion region. Another semiconductor device comprises two gate conductors with enlarged upper portions which merge to create electrically interconnected gate conductors. Methods for forming the above semiconductor devices are also described and claimed.
Claims19
A semiconductor device, comprising:
- a substrate of a first conductivity type;
- a source region of a second conductivity type formed in the substrate proximate an upper surface of the substrate;
- a drain region of the second conductivity type formed in the substrate proximate the upper surface of the substrate and spaced apart from the source region;
- a gate dielectric layer formed on at least a portion of the upper surface of the substrate;
- a raised source feature and a raised drain feature formed on the upper surface of the substrate, the raised source and drain features being electrically connected to the source and drain regions, respectively;
- and
- a gate structure formed on the gate dielectric layer at least partially between the source and drain regions, the gate structure including a lower gate portion formed on the gate dielectric layer and an enlarged upper gate portion supported above the gate dielectric layer by the lower gate portion, the upper gate portion being wider than the lower gate portion;
- wherein the upper gate portion of the gate structure is formed such that at least a portion of the upper gate portion merges with at least one of the raised source and drain features, thereby forming an electrical connection between the gate structure and at least one of the source and drain regions, respectively.
5 more elements
A semiconductor device, comprising:
- a substrate of a first conductivity;
- and
- first and second transistor structures formed on the substrate, each of the first and second transistor structures including a gate dielectric layer formed on an upper surface of the substrate, a lower gate portion formed on the gate dielectric layer, and an enlarged upper gate portion supported above the gate dielectric layer by the lower gate portion, the upper gate portion being wider than the lower gate portion;
- wherein at least a portion of the upper gate portion of the first transistor structure merges with at least a portion of the upper gate portion of the second transistor structure such that the first transistor structure is electrically connected to the second transistor structure.
1 more element
A method for forming a semiconductor device, comprising the steps of:
- forming a substrate of a first conductivity type;
- forming a source region of a second conductivity type in the substrate proximate an upper surface of the substrate;
- forming a drain region of the second conductivity type in the substrate proximate the upper surface of the substrate and spaced apart from the source region;
- forming a gate dielectric layer on at least a portion of the upper surface of the substrate;
- forming a raised source feature and a raised drain feature on the upper surface of the substrate, the raised source and drain features being electrically connected to the source and drain regions, respectively;
- and
- forming a gate structure on the gate dielectric layer at least partially between the source and drain regions, the gate structure including a lower gate portion formed on the gate dielectric layer and an enlarged upper gate portion supported above the gate dielectric layer by the lower gate portion, the upper gate portion being wider than the lower gate portion;
- wherein the upper gate portion of the gate structure is formed such that at least a portion of the upper gate portion merges with at least one of the raised source and drain features, thereby forming an electrical connection between the gate structure and at least one of the source and drain regions, respectively.
5 more elements
A method for forming a semiconductor device, comprising the steps of:
- forming a substrate of a first conductivity;
- and
- forming a first transistor structure and a second transistor structure on the substrate, each transistor structure including a gate dielectric layer formed on an upper surface of the substrate, a lower gate portion formed on the gate dielectric layer, and an enlarged upper gate portion supported above the gate dielectric layer by the lower gate portion, the upper gate portion being wider than the lower gate portion;
- wherein at least a portion of the upper gate portion of the first transistor structure merges with at least a portion of the upper gate portion of the second transistor structure such that the first transistor structure is electrically connected to the second transistor structure.
1 more element
Dependencies are inferred from the claim text.