Method of ultra-low energy ion implantation to form alloy layers in copper
AssigneeAdvanced Micro Devices, Inc.
InventorErcan Adem
Life of this patent
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Abstract
A method of fabricating an integrated circuit can include forming a barrier layer along lateral side walls and a bottom of a via aperture, forming a seed layer proximate and conformal to the barrier layer, and ion implanting elements into the seed layer. The via aperture is configured to receive a via material that electrically connects a first conductive layer and a second conductive layer.
Claims17
A method of fabricating an integrated circuit, the method comprising:
- forming a barrier layer along lateral side walls and a bottom of a via aperture, the via aperture being configured to receive a via material that electrically connects a first conductive layer and a second conductive layer;
- forming a seed layer proximate and conformal to the barrier layer;
- and
- ion implanting elements into the seed layer, wherein the elements can be any one of Zn, Sn, Cr, Ca, Ag, and In, wherein ion implanting elements into the seed layer comprises low energy ion implanting elements into the seed layer, wherein low energy ion implanting comprises implanting at an energy of 0.25 to 2.0 KeV.
A method of implantation after copper seed deposition in an integrated circuit fabrication process, the method comprising:
- providing a first conductive layer over an integrated circuit substrate;
- providing a conformal layer at a bottom and sides of a via aperture positioned over the first conductive layer to form a barrier separating the via aperture from the first conductive layer;
- providing an ultra-low energy ion implant of any one of Zn, Sn, Cr, Ca, Ag, and In to form a seed layer over the conformal layer, wherein ultra-low energy ion implant occurs at an energy level of 0.25 to 2.0 KeV;
- filling the via aperture with a via material;
- and
- providing a second conductive layer over the via material such that the via material electrically connects the first conductive layer to the second conductive layer.
A method of forming a via in an integrated circuit, the method comprising:
- depositing a first conductive layer;
- depositing an etch stop layer over the first conductive layer;
- depositing an insulating layer over the etch stop layer;
- forming an aperture in the insulating layer and the etch stop layer;
- providing a barrier material at a bottom and sides of the aperture to form a barrier layer;
- providing a seed layer over the barrier layer;
- providing a controlled low energy ion implantation of any one of Zn, Sn, Cr, Ca, Ag, and In into the seed layer, wherein low energy ion implantation comprises an energy level of 0.25 to 2.0 KeV;
- filling the aperture with a via material.
Dependencies are inferred from the claim text.