Gate with dual gate dielectric layer and method of fabricating the same

#1. Field of the Invention

#The invention relates to a method for fabricating a gate dielectric layer, and more particularly a dual gate dielectric layer.

#2. Description of the Related Art

#For a better understanding of the present invention, reference is made to a detailed description to be read in conjunction with the accompanying drawings, in which:

#FIGS. 1a to 1e are cross-sections of a conventional method for fabricating a gate with a gate dielectric layer;

#FIGS. 2a to 2l are cross-sections of the method for fabricating a MOS with dual gate dielectric layer of the present invention.

#FIGS. 2a to 2l are cross-sections of the method for fabricating a MOS with dual gate dielectric layer of the present invention.

#In FIG. 2a, a semiconductor substrate 201, such as silicon substrate, is provided, on which a dielectric layer 202, such as pad oxide layer, a hard mask layer 203, such as LPCVD nitride layer, and a patterned photoresist layer 204 with an opening 205 are sequentially formed. The LPCVD nitride layer is deposited using SiCl2H2 and NH3 as reactive gas at 250 to 400° C. The position of the opening 205 is the position of a dual gate dielectric layer in the subsequent process, and the opening 205 exposes the surface of the hard mask layer 203.

#In FIG. 2b, the hard mask layer 203 is etched using the patterned photoresist layer 204 to form an opening in the hard mask layer 203, wherein the opening exposes the surface of the semiconductor substrate 201.